[PATCH] D136847: [RISCV][NFC] Mark rs1 in most memory instructions as memory operand.

[Dmitry via Phabricator via llvm-commits]

dybv-sc added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:505
 class Load_ri<bits<3> funct3, string opcodestr>
-    : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
+    : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPRMemOperand:$rs1, simm12:$imm12),
               opcodestr, "$rd, ${imm12}(${rs1})">;
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jrtc27 wrote:
> So what about all the immediate offsets? OPERAND_MEMORY surely isn't very useful without knowing the offset? It just tells you the instruction is touching memory somewhere in the +/- 2 KiB region centred around that register.
Yes, it is an issue. But there is really not much can be done for immediate. It is not really possible to change it's operand type to OPERAND_MEMORY because the operand type defines their size and signness (and reg operands have their properties defined in RegClass not in type,  so it's safe to change their type). 
However I imagine it to be enough for tools, because I want them to know following: instruction is explicit load/store (mayStore or mayLoad == true is not enough) and their address is based on specific operand marked memory operand(and maybe some other input operands). For example, it may help in llvm-exegesis to produce serial execution for load/store instructions(we can ignore immediate offset here if we assume it to be fixed specific value).


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136847/new/

https://reviews.llvm.org/D136847