[PATCH] D136075: [AArch64]SME2 Multi-vector - Index/Single/Multi Array Vectors LONG INT MLA sources
Paul Walker via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 27 09:01:47 PDT 2022
paulwalker-arm added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td:512
+
+def USMLALL_MZZI : sme2_mla_ll_array_index_32b<"usmlall", 0b001>;
+defm USMLALL_VG2_M2ZZI : sme2_mla_ll_array_vg2_index_32b<"usmlall", 0b100>;
----------------
Despite there being no `_HtoD` variant I think it's worth being consistent and using `_BtoS` for USMLALL and SUMLALL.
================
Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:5431-5437
+ case Match_InvalidMemoryIndexedRange4UImm2:
+ return Error(
+ Loc,
+ "vector select offset must be an immediate range of the form "
+ "<immf>:<imml>, "
+ "where the first immediate is a multiple of 4 in the range [0, 12] "
+ "and the second immediate is immf + 3.");
----------------
I cannot see any tests for this diagnostic.
================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:2101
+ bits<2> Rv;
+ bits<4> i;
+ bits<5> Zn;
----------------
`bits<3>`?
================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:2129
+ bits<4> i;
+ bits<1> imm;
+ let Inst{31-20} = 0b110000010001;
----------------
FYI: You can also use `bit` instead of `bits<1>`.
================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:2288
+
+class sme2_mla_ll_array_vg2_multi<bits<4> op, MatrixOperand matrix_ty,
+ RegisterOperand vector_ty,string mnemonic>
----------------
Please add a comment specifying the encoding group.
================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:2324
+
+class sme2_mla_ll_array_vg4_multi<bits<4> op,MatrixOperand matrix_ty,
+ RegisterOperand vector_ty,
----------------
Please add a comment specifying the encoding group.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D136075/new/
https://reviews.llvm.org/D136075
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