[PATCH] D136713: [SDAG] avoid vector extract/insert around binop

[Sanjay Patel via Phabricator via llvm-commits]

spatel marked 3 inline comments as done.
spatel added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:23548
+    }
+  }
+
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RKSimon wrote:
> dmgreen wrote:
> > RKSimon wrote:
> > > Do we need a isShuffleMaskLegal check?
> > Oh that might be a good idea, some instruction sets like MVE do not have many shuffles. It will depend on the type, it may just be a lane move which is cheap, but may require going through grp regs. I'm not sure there is a lot in it either way though, it might be slow in either case for architectures like that.
> I guess we should always allow idx == 0 as that's effectively what (vt scalar_to_vector(extract_vector_elt(vt x,0))) is
I'll add the legality check. If a target says {0,-1, -1...} is not legal, that seems like a bug for that target since that's an identity (no-op) mask.

In the x86 shift tests that I stepped through, we always shuffle the demanded element down to element 0 before the extract, so we won't actually exercise that extra predicate, but I'll try to find some other case where it happens.


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  https://reviews.llvm.org/D136713/new/

https://reviews.llvm.org/D136713