[PATCH] D136713: [SDAG] avoid vector extract/insert around binop

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:23548
+    }
+  }
+
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dmgreen wrote:
> RKSimon wrote:
> > Do we need a isShuffleMaskLegal check?
> Oh that might be a good idea, some instruction sets like MVE do not have many shuffles. It will depend on the type, it may just be a lane move which is cheap, but may require going through grp regs. I'm not sure there is a lot in it either way though, it might be slow in either case for architectures like that.
I guess we should always allow idx == 0 as that's effectively what (vt scalar_to_vector(extract_vector_elt(vt x,0))) is


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136713/new/

https://reviews.llvm.org/D136713