[PATCH] D124196: [AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs
Pierre van Houtryve via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 26 01:16:56 PDT 2022
Pierre-vh added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1992
+ BuildMI(MBB, MBBI, DL, TII->get(OrSaveExec), Reg).addImm(-1);
+ SaveExec->getOperand(3).setIsDead(); // Mark SCC as dead.
+ }
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Why does SCC need to be dead? What happens if another instruction right after uses it?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D124196/new/
https://reviews.llvm.org/D124196
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