[PATCH] D136678: [AArch64][SVE2] Add the SVE2.1 pext and ptrue predicate-as-counter instructions

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:883
+def PPR_3b : PPRClass<0, 7>; // Restricted 3 bit SVE predicate register class.
+def PPR_3b_p8_p15 : PPRClass<8, 15>;
 
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Given you specify the range does the `_3b` part provide any value? I'd rather just `PPR_p8_p15` or even `PPR_p8to15`.


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Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:71
   SVEDataVector,
+  SMEPredicateAsCounter,
   SVEPredicateVector,
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I see this as more an SVE feature than SME so can this be `SVEPredicateAsCounter`?


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136678/new/

https://reviews.llvm.org/D136678