[PATCH] D136525: [M68k] Add codegen pattern for atomic load / store

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

In D136525#3882193 <https://reviews.llvm.org/D136525#3882193>, @0x59616e wrote:

> In D136525#3880337 <https://reviews.llvm.org/D136525#3880337>, @efriedma wrote:
>
>> Are multi-processor m68k computers a thing?  I can't find any reference to such a thing existing, but the manual indicates that the processor was designed to allow it.  If it does exist, m68k probably needs to use sequences similar to x86.  (x86 didn't have any barrier instruction for a long time, but a "lock" instruction has the right semantics.)
>
> **Take my word with a pinch of salt**
>
> We may have to use the compare-and-swap instruction to reach that (or with the aid of glibc). But is it necessary on such an old architecture that may not have all the modern technologies such as out-of-order execution and store/write buffer --- which are the reasons the atomic instruction or memory barrier exists for ?

Store buffers existed in the era of the m68k, I think.  OOO was mostly later, though.

That said, we shouldn't try to theorycraft the semantics of a system that doesn't actually exist.  I'm okay with assuming we have a single processor if the rest of the ecosystem makes the same assumption (which means we only have to care about interrupts, not memory reordering).


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