[llvm] a4e8492 - [AArch64]SME2 Multi-vector ternary indexed DOT and FMLA instructions
Caroline Concatto via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 25 01:22:37 PDT 2022
Author: Caroline Concatto
Date: 2022-10-25T09:22:16+01:00
New Revision: a4e8492ba2688cab5698ef45efdb7172afee0530
URL: https://github.com/llvm/llvm-project/commit/a4e8492ba2688cab5698ef45efdb7172afee0530
DIFF: https://github.com/llvm/llvm-project/commit/a4e8492ba2688cab5698ef45efdb7172afee0530.diff
LOG: [AArch64]SME2 Multi-vector ternary indexed DOT and FMLA instructions
This patch adds the assembly/disassembly for the following instruction:
FP:
FMLA (multiple and indexed vector): Multi-vector floating-point fused multiply-add by indexed element.
FMLS(multiple and indexed vector): Multi-vector floating-point fused multiply-subtract by indexed element.
BFDOT (multiple and indexed vector): Multi-vector BFloat16 floating-point dot-product by indexed element.
FDOT (multiple and indexed vector): Multi-vector half-precision floating-point dot-product by indexed element.
BFVDOT: Multi-vector BFloat16 floating-point vertical dot-product by indexed element.
FVDOT: Multi-vector half-precision floating-point vertical dot-product by indexed element.
INT:
SDOT (2-way, multiple and indexed vector): Multi-vector signed integer dot-product by indexed element.
(4-way, multiple and indexed vector): Multi-vector signed integer dot-product by indexed element.
SUDOT (multiple and indexed vector): Multi-vector signed by unsigned integer dot-product by indexed elements.
SUVDOT: Multi-vector signed by unsigned integer vertical dot-product by indexed element.
UDOT (2-way, multiple and indexed vector): Multi-vector unsigned integer dot-product by indexed element.
(4-way, multiple and indexed vector): Multi-vector unsigned integer dot-product by indexed element.
USDOT (multiple and indexed vector): Multi-vector unsigned by signed integer dot-product by indexed element.
USVDOT: Multi-vector unsigned by signed integer vertical dot-product by indexed element.
For the multi-vec ternary indexed with 2 and 4 ZA single-vectors for
32 and 64 bits according to the instruction
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Depends on:D135563
Differential Revision: https://reviews.llvm.org/D135676
Added:
llvm/test/MC/AArch64/SME2/bfdot-diagnostics.s
llvm/test/MC/AArch64/SME2/bfdot.s
llvm/test/MC/AArch64/SME2/bfvdot-diagnostics.s
llvm/test/MC/AArch64/SME2/bfvdot.s
llvm/test/MC/AArch64/SME2/fdot-diagnostics.s
llvm/test/MC/AArch64/SME2/fdot.s
llvm/test/MC/AArch64/SME2/fvdot-diagnostics.s
llvm/test/MC/AArch64/SME2/fvdot.s
llvm/test/MC/AArch64/SME2/sdot-diagnostics.s
llvm/test/MC/AArch64/SME2/sdot.s
llvm/test/MC/AArch64/SME2/sudot-diagnostics.s
llvm/test/MC/AArch64/SME2/sudot.s
llvm/test/MC/AArch64/SME2/suvdot-diagnostics.s
llvm/test/MC/AArch64/SME2/suvdot.s
llvm/test/MC/AArch64/SME2/svdot-diagnostics.s
llvm/test/MC/AArch64/SME2/svdot.s
llvm/test/MC/AArch64/SME2/udot-diagnostics.s
llvm/test/MC/AArch64/SME2/udot.s
llvm/test/MC/AArch64/SME2/usdot-diagnostics.s
llvm/test/MC/AArch64/SME2/usdot.s
llvm/test/MC/AArch64/SME2/uvdot-diagnostics.s
llvm/test/MC/AArch64/SME2/uvdot.s
Modified:
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
llvm/lib/Target/AArch64/SMEInstrFormats.td
llvm/test/MC/AArch64/SME2/fmla.s
llvm/test/MC/AArch64/SME2/fmls.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index 5234012e78d4b..9bbcbb46d272a 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -252,11 +252,16 @@ defm FMLA_VG2_M2ZZ_S : sme2_mla_add_sub_array_vg2_single_S<"fmla", 0b00>;
defm FMLA_VG4_M4ZZ_S : sme2_mla_add_sub_array_vg4_single_S<"fmla", 0b00>;
defm FMLA_VG2_M2Z2Z_S : sme2_mla_add_sub_array_vg2_multi_S<"fmla", 0b00>;
defm FMLA_VG4_M4Z4Z_S : sme2_mla_add_sub_array_vg4_multi_S<"fmla", 0b00>;
+defm FMLA_VG2_M2ZZI_S : sme2_multi_vec_array_vg2_index_32b<"fmla", 0b0000, ZZ_s_mul_r, ZPR4b32>;
+defm FMLA_VG4_M4ZZI_S : sme2_multi_vec_array_vg4_index_32b<"fmla", 0b0000, ZZZZ_s_mul_r, ZPR4b32>;
defm FMLS_VG2_M2ZZ_S : sme2_mla_add_sub_array_vg2_single_S<"fmls", 0b01>;
defm FMLS_VG4_M4ZZ_S : sme2_mla_add_sub_array_vg4_single_S<"fmls", 0b01>;
defm FMLS_VG2_M2Z2Z_S : sme2_mla_add_sub_array_vg2_multi_S<"fmls", 0b01>;
defm FMLS_VG4_M4Z4Z_S : sme2_mla_add_sub_array_vg4_multi_S<"fmls", 0b01>;
+defm FMLS_VG2_M2ZZI_S : sme2_multi_vec_array_vg2_index_32b<"fmls", 0b0010, ZZ_s_mul_r, ZPR4b32>;
+defm FMLS_VG4_M4ZZI_S : sme2_multi_vec_array_vg4_index_32b<"fmls", 0b0010, ZZZZ_s_mul_r, ZPR4b32>;
+
defm ADDA_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"add", 0b10>;
defm ADDA_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"add", 0b10>;
@@ -429,6 +434,41 @@ defm SCLAMP_VG4_4Z4Z : sme2_int_clamp_vector_vg4_multi<"sclamp", 0b0>;
defm UCLAMP_VG2_2Z2Z : sme2_int_clamp_vector_vg2_multi<"uclamp", 0b1>;
defm UCLAMP_VG4_4Z4Z : sme2_int_clamp_vector_vg4_multi<"uclamp", 0b1>;
+defm FDOT_VG2_M2ZZI_HtoS : sme2_multi_vec_array_vg2_index_32b<"fdot", 0b1001, ZZ_h_mul_r, ZPR4b16>;
+defm FDOT_VG4_M4ZZI_HtoS : sme2_multi_vec_array_vg4_index_32b<"fdot", 0b1001, ZZZZ_h_mul_r, ZPR4b16>;
+
+defm BFDOT_VG2_M2ZZI_HtoS : sme2_multi_vec_array_vg2_index_32b<"bfdot", 0b1011, ZZ_h_mul_r, ZPR4b16>;
+defm BFDOT_VG4_M4ZZI_HtoS : sme2_multi_vec_array_vg4_index_32b<"bfdot", 0b1011, ZZZZ_h_mul_r, ZPR4b16>;
+
+defm BFVDOT_VG2_M2ZZI_HtoS : sme2_multi_vec_array_vg2_index_32b<"bfvdot", 0b0011, ZZ_h_mul_r, ZPR4b16>;
+
+defm FVDOT_VG2_M2ZZI_HtoS : sme2_multi_vec_array_vg2_index_32b<"fvdot", 0b0001, ZZ_h_mul_r, ZPR4b16>;
+
+defm SDOT_VG2_M2ZZI_HToS : sme2_multi_vec_array_vg2_index_32b<"sdot", 0b1000, ZZ_h_mul_r, ZPR4b16>;
+defm SDOT_VG2_M2ZZI_BToS : sme2_multi_vec_array_vg2_index_32b<"sdot", 0b1100, ZZ_b_mul_r, ZPR4b8>;
+defm SDOT_VG4_M4ZZI_HToS : sme2_multi_vec_array_vg4_index_32b<"sdot", 0b1000, ZZZZ_h_mul_r, ZPR4b16>;
+defm SDOT_VG4_M4ZZI_BToS : sme2_multi_vec_array_vg4_index_32b<"sdot", 0b1100, ZZZZ_b_mul_r, ZPR4b8>;
+
+defm SUDOT_VG2_M2ZZI_BToS : sme2_multi_vec_array_vg2_index_32b<"sudot", 0b1111, ZZ_b_mul_r, ZPR4b8>;
+defm SUDOT_VG4_M4ZZI_BToS : sme2_multi_vec_array_vg4_index_32b<"sudot", 0b1111, ZZZZ_b_mul_r, ZPR4b8>;
+
+defm SVDOT_VG2_M2ZZI_HtoS : sme2_multi_vec_array_vg2_index_32b<"svdot", 0b0100, ZZ_h_mul_r, ZPR4b16>;
+defm SVDOT_VG4_M4ZZI_BtoS : sme2_multi_vec_array_vg4_index_32b<"svdot", 0b0100, ZZZZ_b_mul_r, ZPR4b8>;
+
+defm SUVDOT_VG4_M4ZZI_BToS : sme2_multi_vec_array_vg4_index_32b<"suvdot", 0b0111, ZZZZ_b_mul_r, ZPR4b8>;
+
+defm UDOT_VG2_M2ZZI_HToS : sme2_multi_vec_array_vg2_index_32b<"udot", 0b1010, ZZ_h_mul_r, ZPR4b16>;
+defm UDOT_VG2_M2ZZI_BToS : sme2_multi_vec_array_vg2_index_32b<"udot", 0b1110, ZZ_b_mul_r, ZPR4b8>;
+defm UDOT_VG4_M4ZZI_BtoS : sme2_multi_vec_array_vg4_index_32b<"udot", 0b1110, ZZZZ_b_mul_r, ZPR4b8>;
+defm UDOT_VG4_M4ZZI_HToS : sme2_multi_vec_array_vg4_index_32b<"udot", 0b1010, ZZZZ_h_mul_r, ZPR4b16>;
+
+defm USDOT_VG2_M2ZZI_BToS : sme2_multi_vec_array_vg2_index_32b<"usdot", 0b1101, ZZ_b_mul_r, ZPR4b8>;
+defm USDOT_VG4_M4ZZI_BToS : sme2_multi_vec_array_vg4_index_32b<"usdot", 0b1101, ZZZZ_b_mul_r, ZPR4b8>;
+
+defm USVDOT_VG4_M4ZZI_BToS : sme2_multi_vec_array_vg4_index_32b<"usvdot", 0b0101, ZZZZ_b_mul_r, ZPR4b8>;
+
+defm UVDOT_VG2_M2ZZI_HtoS : sme2_multi_vec_array_vg2_index_32b<"uvdot", 0b0110, ZZ_h_mul_r, ZPR4b16>;
+defm UVDOT_VG4_M4ZZI_BtoS : sme2_multi_vec_array_vg4_index_32b<"uvdot", 0b0110, ZZZZ_b_mul_r, ZPR4b8>;
}
@@ -449,6 +489,16 @@ defm ADDA_VG4_M4Z4Z_D : sme2_multivec_accum_add_sub_vg4_D<"add", 0b10>;
defm SUBA_VG2_M2Z2Z_D : sme2_multivec_accum_add_sub_vg2_D<"sub", 0b11>;
defm SUBA_VG4_M4Z4Z_D : sme2_multivec_accum_add_sub_vg4_D<"sub", 0b11>;
+
+defm SDOT_VG2_M2ZZI_HtoD : sme2_multi_vec_array_vg2_index_64b<"sdot", 0b01, ZZ_h_mul_r, ZPR4b16>;
+defm SDOT_VG4_M4ZZI_HtoD : sme2_multi_vec_array_vg4_index_64b<"sdot", 0b001, ZZZZ_h_mul_r, ZPR4b16>;
+
+defm SVDOT_VG4_M4ZZI_HtoD : sme2_multi_vec_array_vg4_index_64b<"svdot", 0b101, ZZZZ_h_mul_r, ZPR4b16>;
+
+defm UDOT_VG2_M2ZZI_HtoD : sme2_multi_vec_array_vg2_index_64b<"udot", 0b11, ZZ_h_mul_r, ZPR4b16>;
+defm UDOT_VG4_M4ZZI_HtoD : sme2_multi_vec_array_vg4_index_64b<"udot", 0b011, ZZZZ_h_mul_r, ZPR4b16>;
+
+defm UVDOT_VG4_M4ZZI_HtoD : sme2_multi_vec_array_vg4_index_64b<"uvdot", 0b111, ZZZZ_h_mul_r, ZPR4b16>;
}
let Predicates = [HasSME2, HasSMEF64F64] in {
@@ -456,11 +506,15 @@ defm FMLA_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"fmla", 0b00>;
defm FMLA_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"fmla", 0b00>;
defm FMLA_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"fmla", 0b00>;
defm FMLA_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"fmla", 0b00>;
+defm FMLA_VG2_M2ZZI_D : sme2_multi_vec_array_vg2_index_64b<"fmla", 0b00, ZZ_d_mul_r, ZPR4b64>;
+defm FMLA_VG4_M4ZZI_D : sme2_multi_vec_array_vg4_index_64b<"fmla", 0b000, ZZZZ_d_mul_r, ZPR4b64>;
defm FMLS_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"fmls", 0b01>;
defm FMLS_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"fmls", 0b01>;
defm FMLS_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"fmls", 0b01>;
defm FMLS_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"fmls", 0b01>;
+defm FMLS_VG2_M2ZZI_D : sme2_multi_vec_array_vg2_index_64b<"fmls", 0b10, ZZ_d_mul_r, ZPR4b64>;
+defm FMLS_VG4_M4ZZI_D : sme2_multi_vec_array_vg4_index_64b<"fmls", 0b010, ZZZZ_d_mul_r, ZPR4b64>;
defm FADD_VG2_M2Z2Z_D : sme2_multivec_accum_add_sub_vg2_D<"fadd", 0b00>;
defm FADD_VG4_M4Z4Z_D : sme2_multivec_accum_add_sub_vg4_D<"fadd", 0b00>;
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index 29450032c86de..4ef8168683ebb 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -1929,3 +1929,169 @@ multiclass sme2_int_clamp_vector_vg4_multi<string mnemonic, bit u>{
def _S : sme2_clamp_vector_vg4_multi<0b10, 0b11, u, ZZZZ_s_mul_r, ZPR32, mnemonic>;
def _D : sme2_clamp_vector_vg4_multi<0b11, 0b11, u, ZZZZ_d_mul_r, ZPR64, mnemonic>;
}
+
+//===----------------------------------------------------------------------===//
+// SME2 Dot Products and MLA
+
+// SME2 multi-vec ternary indexed two registers 32-bit
+class sme2_multi_vec_array_vg2_index_32b<bits<4> op,
+ RegisterOperand multi_vector_ty,
+ ZPRRegOp vector_ty,
+ string mnemonic>
+ : I<(outs MatrixOp32:$ZAda),
+ (ins MatrixOp32:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3,
+ multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexS:$i2),
+ mnemonic, "\t$ZAda[$Rv, $imm3, vgx2], $Zn, $Zm$i2",
+ "", []>, Sched<[]> {
+ bits<4> Zm;
+ bits<2> Rv;
+ bits<2> i2;
+ bits<4> Zn;
+ bits<3> imm3;
+ let Inst{31-20} = 0b110000010101;
+ let Inst{19-16} = Zm;
+ let Inst{15} = 0b0;
+ let Inst{14-13} = Rv;
+ let Inst{12} = op{3};
+ let Inst{11-10} = i2;
+ let Inst{9-6} = Zn;
+ let Inst{5-3} = op{2-0};
+ let Inst{2-0} = imm3;
+
+ let Constraints = "$ZAda = $_ZAda";
+}
+
+multiclass sme2_multi_vec_array_vg2_index_32b<string mnemonic, bits<4> op,
+ RegisterOperand multi_vector_ty,
+ ZPRRegOp vector_ty> {
+ def NAME : sme2_multi_vec_array_vg2_index_32b<op, multi_vector_ty, vector_ty,
+ mnemonic>;
+
+ def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm3], $Zn, $Zm$i2",
+ (!cast<Instruction>(NAME) MatrixOp32:$ZAda, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3,
+ multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexS:$i2), 0>;
+}
+
+// SME2 multi-vec ternary indexed two registers 64-bit
+
+class sme2_multi_vec_array_vg2_index_64b<bits<2> op,
+ RegisterOperand multi_vector_ty,
+ ZPRRegOp vector_ty,
+ string mnemonic>
+ : I<(outs MatrixOp64:$ZAda),
+ (ins MatrixOp64:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3,
+ multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexD:$i1),
+ mnemonic, "\t$ZAda[$Rv, $imm3, vgx2], $Zn, $Zm$i1",
+ "", []>, Sched<[]> {
+ bits<4> Zm;
+ bits<2> Rv;
+ bits<1> i1;
+ bits<4> Zn;
+ bits<3> imm3;
+ let Inst{31-20} = 0b110000011101;
+ let Inst{19-16} = Zm;
+ let Inst{15} = 0b0;
+ let Inst{14-13} = Rv;
+ let Inst{12-11} = 0b00;
+ let Inst{10} = i1;
+ let Inst{9-6} = Zn;
+ let Inst{5} = 0b0;
+ let Inst{4-3} = op;
+ let Inst{2-0} = imm3;
+
+ let Constraints = "$ZAda = $_ZAda";
+}
+
+multiclass sme2_multi_vec_array_vg2_index_64b<string mnemonic, bits<2> op,
+ RegisterOperand multi_vector_ty,
+ ZPRRegOp vector_ty> {
+ def NAME : sme2_multi_vec_array_vg2_index_64b<op, multi_vector_ty, vector_ty,
+ mnemonic>;
+
+ def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm3], $Zn, $Zm$i1",
+ (!cast<Instruction>(NAME) MatrixOp64:$ZAda, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3,
+ multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexD:$i1), 0>;
+}
+
+// SME2 multi-vec ternary indexed four registers 32-bit
+
+class sme2_multi_vec_array_vg4_index_32b<bits<4> op,
+ RegisterOperand multi_vector_ty,
+ ZPRRegOp vector_ty,
+ string mnemonic>
+ : I<(outs MatrixOp32:$ZAda),
+ (ins MatrixOp32:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3,
+ multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexS:$i2),
+ mnemonic, "\t$ZAda[$Rv, $imm3, vgx4], $Zn, $Zm$i2",
+ "", []>, Sched<[]> {
+ bits<4> Zm;
+ bits<2> Rv;
+ bits<2> i2;
+ bits<3> Zn;
+ bits<3> imm3;
+ let Inst{31-20} = 0b110000010101;
+ let Inst{19-16} = Zm;
+ let Inst{15} = 0b1;
+ let Inst{14-13} = Rv;
+ let Inst{12} = op{3};
+ let Inst{11-10} = i2;
+ let Inst{9-7} = Zn;
+ let Inst{6} = 0b0;
+ let Inst{5-3} = op{2-0};
+ let Inst{2-0} = imm3;
+
+ let Constraints = "$ZAda = $_ZAda";
+}
+
+multiclass sme2_multi_vec_array_vg4_index_32b<string mnemonic, bits<4> op,
+ RegisterOperand multi_vector_ty,
+ ZPRRegOp vector_ty> {
+ def NAME : sme2_multi_vec_array_vg4_index_32b<op, multi_vector_ty, vector_ty,
+ mnemonic>;
+
+ def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm3], $Zn, $Zm$i2",
+ (!cast<Instruction>(NAME) MatrixOp32:$ZAda, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3,
+ multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexS:$i2), 0>;
+}
+
+// SME2 multi-vec ternary indexed four registers 64-bit
+class sme2_multi_vec_array_vg4_index_64b<bits<3> op,
+ RegisterOperand multi_vector_ty,
+ ZPRRegOp vector_ty,
+ string mnemonic>
+ : I<(outs MatrixOp64:$ZAda),
+ (ins MatrixOp64:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3,
+ multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexD:$i1),
+ mnemonic, "\t$ZAda[$Rv, $imm3, vgx4], $Zn, $Zm$i1",
+ "", []>, Sched<[]> {
+ bits<4> Zm;
+ bits<2> Rv;
+ bits<1> i1;
+ bits<3> Zn;
+ bits<3> imm3;
+ let Inst{31-20} = 0b110000011101;
+ let Inst{19-16} = Zm;
+ let Inst{15} = 0b1;
+ let Inst{14-13} = Rv;
+ let Inst{12} = 0b0;
+ let Inst{11} = op{2};
+ let Inst{10} = i1;
+ let Inst{9-7} = Zn;
+ let Inst{6-5} = 0b00;
+ let Inst{4-3} = op{1-0};
+ let Inst{2-0} = imm3;
+
+ let Constraints = "$ZAda = $_ZAda";
+}
+
+multiclass sme2_multi_vec_array_vg4_index_64b<string mnemonic, bits<3> op,
+ RegisterOperand multi_vector_ty,
+ ZPRRegOp vector_ty> {
+ def NAME : sme2_multi_vec_array_vg4_index_64b<op, multi_vector_ty, vector_ty,
+ mnemonic>;
+
+ def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm3], $Zn, $Zm$i1",
+ (!cast<Instruction>(NAME) MatrixOp64:$ZAda, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3,
+ multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexD:$i1), 0>;
+}
+
diff --git a/llvm/test/MC/AArch64/SME2/bfdot-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfdot-diagnostics.s
new file mode 100644
index 0000000000000..df1a0493ecfd2
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/bfdot-diagnostics.s
@@ -0,0 +1,52 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+bfdot za.s[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfdot za.s[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+bfdot za.s[w12, 0, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: bfdot za.s[w12, 0, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select offset
+
+bfdot za.s[w8, -1, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: bfdot za.s[w8, -1, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfdot za.s[w8, 8, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: bfdot za.s[w8, 8, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+bfdot za.h[w8, 0, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: bfdot za.h[w8, 0, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane index
+
+bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z0.h[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z0.h[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z0.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z0.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/bfdot.s b/llvm/test/MC/AArch64/SME2/bfdot.s
new file mode 100644
index 0000000000000..711c3f32bf2e5
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/bfdot.s
@@ -0,0 +1,303 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+bfdot za.s[w8, 0, vgx2], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00010000-00011000
+// CHECK-INST: bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501018 <unknown>
+
+bfdot za.s[w8, 0], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00010000-00011000
+// CHECK-INST: bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501018 <unknown>
+
+bfdot za.s[w10, 5, vgx2], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01010101-01011101
+// CHECK-INST: bfdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x5d,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155555d <unknown>
+
+bfdot za.s[w10, 5], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01010101-01011101
+// CHECK-INST: bfdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x5d,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155555d <unknown>
+
+bfdot za.s[w11, 7, vgx2], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01111101-10011111
+// CHECK-INST: bfdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0x9f,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587d9f <unknown>
+
+bfdot za.s[w11, 7], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01111101-10011111
+// CHECK-INST: bfdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0x9f,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587d9f <unknown>
+
+bfdot za.s[w11, 7, vgx2], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01111111-11011111
+// CHECK-INST: bfdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xdf,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7fdf <unknown>
+
+bfdot za.s[w11, 7], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01111111-11011111
+// CHECK-INST: bfdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xdf,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7fdf <unknown>
+
+bfdot za.s[w8, 5, vgx2], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00011110-00011101
+// CHECK-INST: bfdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x1d,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e1d <unknown>
+
+bfdot za.s[w8, 5], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00011110-00011101
+// CHECK-INST: bfdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x1d,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e1d <unknown>
+
+bfdot za.s[w8, 1, vgx2], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00010100-00011001
+// CHECK-INST: bfdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x19,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1419 <unknown>
+
+bfdot za.s[w8, 1], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00010100-00011001
+// CHECK-INST: bfdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x19,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1419 <unknown>
+
+bfdot za.s[w10, 0, vgx2], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01010110-01011000
+// CHECK-INST: bfdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x58,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545658 <unknown>
+
+bfdot za.s[w10, 0], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01010110-01011000
+// CHECK-INST: bfdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x58,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545658 <unknown>
+
+bfdot za.s[w8, 0, vgx2], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00011001-10011000
+// CHECK-INST: bfdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0x98,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1521998 <unknown>
+
+bfdot za.s[w8, 0], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00011001-10011000
+// CHECK-INST: bfdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0x98,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1521998 <unknown>
+
+bfdot za.s[w10, 1, vgx2], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01011000-00011001
+// CHECK-INST: bfdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x19,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5819 <unknown>
+
+bfdot za.s[w10, 1], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01011000-00011001
+// CHECK-INST: bfdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x19,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5819 <unknown>
+
+bfdot za.s[w8, 5, vgx2], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00011010-11011101
+// CHECK-INST: bfdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xdd,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1add <unknown>
+
+bfdot za.s[w8, 5], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00011010-11011101
+// CHECK-INST: bfdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xdd,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1add <unknown>
+
+bfdot za.s[w11, 2, vgx2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01110101-00011010
+// CHECK-INST: bfdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x1a,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151751a <unknown>
+
+bfdot za.s[w11, 2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01110101-00011010
+// CHECK-INST: bfdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x1a,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151751a <unknown>
+
+bfdot za.s[w9, 7, vgx2], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00111001-10011111
+// CHECK-INST: bfdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0x9f,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b399f <unknown>
+
+bfdot za.s[w9, 7], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00111001-10011111
+// CHECK-INST: bfdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0x9f,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b399f <unknown>
+
+
+bfdot za.s[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0] // 11000001-01010000-10010000-00011000
+// CHECK-INST: bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509018 <unknown>
+
+bfdot za.s[w8, 0], {z0.h - z3.h}, z0.h[0] // 11000001-01010000-10010000-00011000
+// CHECK-INST: bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509018 <unknown>
+
+bfdot za.s[w10, 5, vgx4], {z8.h - z11.h}, z5.h[1] // 11000001-01010101-11010101-00011101
+// CHECK-INST: bfdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x1d,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d51d <unknown>
+
+bfdot za.s[w10, 5], {z8.h - z11.h}, z5.h[1] // 11000001-01010101-11010101-00011101
+// CHECK-INST: bfdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x1d,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d51d <unknown>
+
+bfdot za.s[w11, 7, vgx4], {z12.h - z15.h}, z8.h[3] // 11000001-01011000-11111101-10011111
+// CHECK-INST: bfdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]
+// CHECK-ENCODING: [0x9f,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fd9f <unknown>
+
+bfdot za.s[w11, 7], {z12.h - z15.h}, z8.h[3] // 11000001-01011000-11111101-10011111
+// CHECK-INST: bfdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]
+// CHECK-ENCODING: [0x9f,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fd9f <unknown>
+
+bfdot za.s[w11, 7, vgx4], {z28.h - z31.h}, z15.h[3] // 11000001-01011111-11111111-10011111
+// CHECK-INST: bfdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]
+// CHECK-ENCODING: [0x9f,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fff9f <unknown>
+
+bfdot za.s[w11, 7], {z28.h - z31.h}, z15.h[3] // 11000001-01011111-11111111-10011111
+// CHECK-INST: bfdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]
+// CHECK-ENCODING: [0x9f,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fff9f <unknown>
+
+bfdot za.s[w8, 5, vgx4], {z16.h - z19.h}, z0.h[3] // 11000001-01010000-10011110-00011101
+// CHECK-INST: bfdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]
+// CHECK-ENCODING: [0x1d,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e1d <unknown>
+
+bfdot za.s[w8, 5], {z16.h - z19.h}, z0.h[3] // 11000001-01010000-10011110-00011101
+// CHECK-INST: bfdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]
+// CHECK-ENCODING: [0x1d,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e1d <unknown>
+
+bfdot za.s[w8, 1, vgx4], {z0.h - z3.h}, z14.h[1] // 11000001-01011110-10010100-00011001
+// CHECK-INST: bfdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x19,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9419 <unknown>
+
+bfdot za.s[w8, 1], {z0.h - z3.h}, z14.h[1] // 11000001-01011110-10010100-00011001
+// CHECK-INST: bfdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x19,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9419 <unknown>
+
+bfdot za.s[w10, 0, vgx4], {z16.h - z19.h}, z4.h[1] // 11000001-01010100-11010110-00011000
+// CHECK-INST: bfdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x18,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d618 <unknown>
+
+bfdot za.s[w10, 0], {z16.h - z19.h}, z4.h[1] // 11000001-01010100-11010110-00011000
+// CHECK-INST: bfdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x18,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d618 <unknown>
+
+bfdot za.s[w8, 0, vgx4], {z12.h - z15.h}, z2.h[2] // 11000001-01010010-10011001-10011000
+// CHECK-INST: bfdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]
+// CHECK-ENCODING: [0x98,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1529998 <unknown>
+
+bfdot za.s[w8, 0], {z12.h - z15.h}, z2.h[2] // 11000001-01010010-10011001-10011000
+// CHECK-INST: bfdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]
+// CHECK-ENCODING: [0x98,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1529998 <unknown>
+
+bfdot za.s[w10, 1, vgx4], {z0.h - z3.h}, z10.h[2] // 11000001-01011010-11011000-00011001
+// CHECK-INST: bfdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]
+// CHECK-ENCODING: [0x19,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad819 <unknown>
+
+bfdot za.s[w10, 1], {z0.h - z3.h}, z10.h[2] // 11000001-01011010-11011000-00011001
+// CHECK-INST: bfdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]
+// CHECK-ENCODING: [0x19,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad819 <unknown>
+
+bfdot za.s[w8, 5, vgx4], {z20.h - z23.h}, z14.h[2] // 11000001-01011110-10011010-10011101
+// CHECK-INST: bfdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]
+// CHECK-ENCODING: [0x9d,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9a9d <unknown>
+
+bfdot za.s[w8, 5], {z20.h - z23.h}, z14.h[2] // 11000001-01011110-10011010-10011101
+// CHECK-INST: bfdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]
+// CHECK-ENCODING: [0x9d,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9a9d <unknown>
+
+bfdot za.s[w11, 2, vgx4], {z8.h - z11.h}, z1.h[1] // 11000001-01010001-11110101-00011010
+// CHECK-INST: bfdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x1a,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f51a <unknown>
+
+bfdot za.s[w11, 2], {z8.h - z11.h}, z1.h[1] // 11000001-01010001-11110101-00011010
+// CHECK-INST: bfdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x1a,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f51a <unknown>
+
+bfdot za.s[w9, 7, vgx4], {z12.h - z15.h}, z11.h[2] // 11000001-01011011-10111001-10011111
+// CHECK-INST: bfdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]
+// CHECK-ENCODING: [0x9f,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb99f <unknown>
+
+bfdot za.s[w9, 7], {z12.h - z15.h}, z11.h[2] // 11000001-01011011-10111001-10011111
+// CHECK-INST: bfdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]
+// CHECK-ENCODING: [0x9f,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb99f <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/bfvdot-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfvdot-diagnostics.s
new file mode 100644
index 0000000000000..434c3a616fc50
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/bfvdot-diagnostics.s
@@ -0,0 +1,64 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Out of range index offset
+
+bfvdot za.s[w8, 8, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: bfvdot za.s[w8, 8, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfvdot za.s[w8, -1, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: bfvdot za.s[w8, -1, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+bfvdot za.s[w7, 0, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: bfvdot za.s[w7, 0, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfvdot za.s[w12, 0, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: bfvdot za.s[w12, 0, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+bfvdot za.s[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfvdot za.s[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfvdot za.s[w8, 0, vgx2], {z1.h-z2.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: bfvdot za.s[w8, 0, vgx2], {z1.h-z2.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Matrix Operand
+
+bfvdot za.h[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: bfvdot za.h[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector grouping
+
+bfvdot za.s[w8, 0, vgx4], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfvdot za.s[w8, 0, vgx4], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid lane index
+
+bfvdot za.s[w8, 0, vgx2], {z0.h-z1.h}, z0.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]
+// CHECK-NEXT: bfvdot za.s[w8, 0, vgx2], {z0.h-z1.h}, z0.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/bfvdot.s b/llvm/test/MC/AArch64/SME2/bfvdot.s
new file mode 100644
index 0000000000000..31f2f717408b3
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/bfvdot.s
@@ -0,0 +1,158 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+bfvdot za.s[w8, 0, vgx2], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00000000-00011000
+// CHECK-INST: bfvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x00,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500018 <unknown>
+
+bfvdot za.s[w8, 0], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00000000-00011000
+// CHECK-INST: bfvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x00,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500018 <unknown>
+
+bfvdot za.s[w10, 5, vgx2], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01000101-01011101
+// CHECK-INST: bfvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x5d,0x45,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155455d <unknown>
+
+bfvdot za.s[w10, 5], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01000101-01011101
+// CHECK-INST: bfvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x5d,0x45,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155455d <unknown>
+
+bfvdot za.s[w11, 7, vgx2], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01101101-10011111
+// CHECK-INST: bfvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0x9f,0x6d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1586d9f <unknown>
+
+bfvdot za.s[w11, 7], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01101101-10011111
+// CHECK-INST: bfvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0x9f,0x6d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1586d9f <unknown>
+
+bfvdot za.s[w11, 7, vgx2], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01101111-11011111
+// CHECK-INST: bfvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xdf,0x6f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f6fdf <unknown>
+
+bfvdot za.s[w11, 7], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01101111-11011111
+// CHECK-INST: bfvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xdf,0x6f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f6fdf <unknown>
+
+bfvdot za.s[w8, 5, vgx2], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00001110-00011101
+// CHECK-INST: bfvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x1d,0x0e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500e1d <unknown>
+
+bfvdot za.s[w8, 5], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00001110-00011101
+// CHECK-INST: bfvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x1d,0x0e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500e1d <unknown>
+
+bfvdot za.s[w8, 1, vgx2], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00000100-00011001
+// CHECK-INST: bfvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x19,0x04,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0419 <unknown>
+
+bfvdot za.s[w8, 1], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00000100-00011001
+// CHECK-INST: bfvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x19,0x04,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0419 <unknown>
+
+bfvdot za.s[w10, 0, vgx2], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01000110-01011000
+// CHECK-INST: bfvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x58,0x46,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1544658 <unknown>
+
+bfvdot za.s[w10, 0], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01000110-01011000
+// CHECK-INST: bfvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x58,0x46,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1544658 <unknown>
+
+bfvdot za.s[w8, 0, vgx2], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00001001-10011000
+// CHECK-INST: bfvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0x98,0x09,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1520998 <unknown>
+
+bfvdot za.s[w8, 0], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00001001-10011000
+// CHECK-INST: bfvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0x98,0x09,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1520998 <unknown>
+
+bfvdot za.s[w10, 1, vgx2], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01001000-00011001
+// CHECK-INST: bfvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x19,0x48,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a4819 <unknown>
+
+bfvdot za.s[w10, 1], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01001000-00011001
+// CHECK-INST: bfvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x19,0x48,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a4819 <unknown>
+
+bfvdot za.s[w8, 5, vgx2], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00001010-11011101
+// CHECK-INST: bfvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xdd,0x0a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0add <unknown>
+
+bfvdot za.s[w8, 5], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00001010-11011101
+// CHECK-INST: bfvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xdd,0x0a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0add <unknown>
+
+bfvdot za.s[w11, 2, vgx2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01100101-00011010
+// CHECK-INST: bfvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x1a,0x65,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151651a <unknown>
+
+bfvdot za.s[w11, 2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01100101-00011010
+// CHECK-INST: bfvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x1a,0x65,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151651a <unknown>
+
+bfvdot za.s[w9, 7, vgx2], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00101001-10011111
+// CHECK-INST: bfvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0x9f,0x29,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b299f <unknown>
+
+bfvdot za.s[w9, 7], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00101001-10011111
+// CHECK-INST: bfvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0x9f,0x29,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b299f <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/fdot-diagnostics.s b/llvm/test/MC/AArch64/SME2/fdot-diagnostics.s
new file mode 100644
index 0000000000000..819b5a12a56b4
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fdot-diagnostics.s
@@ -0,0 +1,53 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid select register
+
+fdot za.s[w7, 0, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: fdot za.s[w7, 0, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fdot za.s[w12, 0, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: fdot za.s[w12, 0, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid select offset
+
+fdot za.s[w8, 8], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: fdot za.s[w8, 8], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fdot za.s[w8, -1], {z0.h-z3.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: fdot za.s[w8, -1], {z0.h-z3.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Out of range element index
+
+fdot za.s[w8, 0], {z0.h-z1.h}, z0.h[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: fdot za.s[w8, 0], {z0.h-z1.h}, z0.h[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fdot za.s[w8, 0], {z0.h-z3.h}, z0.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: fdot za.s[w8, 0], {z0.h-z3.h}, z0.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// ZPR range constraint
+
+fdot za.s[w8, 5], {z0.h-z1.h}, z16.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fdot za.s[w8, 5], {z0.h-z1.h}, z16.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fdot za.s[w8, 5], {z0.h-z3.h}, z16.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: fdot za.s[w8, 5], {z0.h-z3.h}, z16.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/fdot.s b/llvm/test/MC/AArch64/SME2/fdot.s
new file mode 100644
index 0000000000000..115962cedf0b5
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fdot.s
@@ -0,0 +1,303 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fdot za.s[w8, 0, vgx2], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00010000-00001000
+// CHECK-INST: fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501008 <unknown>
+
+fdot za.s[w8, 0], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00010000-00001000
+// CHECK-INST: fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501008 <unknown>
+
+fdot za.s[w10, 5, vgx2], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01010101-01001101
+// CHECK-INST: fdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x4d,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155554d <unknown>
+
+fdot za.s[w10, 5], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01010101-01001101
+// CHECK-INST: fdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x4d,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155554d <unknown>
+
+fdot za.s[w11, 7, vgx2], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01111101-10001111
+// CHECK-INST: fdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0x8f,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587d8f <unknown>
+
+fdot za.s[w11, 7], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01111101-10001111
+// CHECK-INST: fdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0x8f,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587d8f <unknown>
+
+fdot za.s[w11, 7, vgx2], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01111111-11001111
+// CHECK-INST: fdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xcf,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7fcf <unknown>
+
+fdot za.s[w11, 7], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01111111-11001111
+// CHECK-INST: fdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xcf,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7fcf <unknown>
+
+fdot za.s[w8, 5, vgx2], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00011110-00001101
+// CHECK-INST: fdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x0d,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e0d <unknown>
+
+fdot za.s[w8, 5], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00011110-00001101
+// CHECK-INST: fdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x0d,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e0d <unknown>
+
+fdot za.s[w8, 1, vgx2], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00010100-00001001
+// CHECK-INST: fdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x09,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1409 <unknown>
+
+fdot za.s[w8, 1], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00010100-00001001
+// CHECK-INST: fdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x09,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1409 <unknown>
+
+fdot za.s[w10, 0, vgx2], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01010110-01001000
+// CHECK-INST: fdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x48,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545648 <unknown>
+
+fdot za.s[w10, 0], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01010110-01001000
+// CHECK-INST: fdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x48,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545648 <unknown>
+
+fdot za.s[w8, 0, vgx2], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00011001-10001000
+// CHECK-INST: fdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0x88,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1521988 <unknown>
+
+fdot za.s[w8, 0], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00011001-10001000
+// CHECK-INST: fdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0x88,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1521988 <unknown>
+
+fdot za.s[w10, 1, vgx2], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01011000-00001001
+// CHECK-INST: fdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x09,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5809 <unknown>
+
+fdot za.s[w10, 1], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01011000-00001001
+// CHECK-INST: fdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x09,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5809 <unknown>
+
+fdot za.s[w8, 5, vgx2], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00011010-11001101
+// CHECK-INST: fdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xcd,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1acd <unknown>
+
+fdot za.s[w8, 5], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00011010-11001101
+// CHECK-INST: fdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xcd,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1acd <unknown>
+
+fdot za.s[w11, 2, vgx2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01110101-00001010
+// CHECK-INST: fdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x0a,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151750a <unknown>
+
+fdot za.s[w11, 2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01110101-00001010
+// CHECK-INST: fdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x0a,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151750a <unknown>
+
+fdot za.s[w9, 7, vgx2], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00111001-10001111
+// CHECK-INST: fdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0x8f,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b398f <unknown>
+
+fdot za.s[w9, 7], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00111001-10001111
+// CHECK-INST: fdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0x8f,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b398f <unknown>
+
+
+fdot za.s[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0] // 11000001-01010000-10010000-00001000
+// CHECK-INST: fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509008 <unknown>
+
+fdot za.s[w8, 0], {z0.h - z3.h}, z0.h[0] // 11000001-01010000-10010000-00001000
+// CHECK-INST: fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509008 <unknown>
+
+fdot za.s[w10, 5, vgx4], {z8.h - z11.h}, z5.h[1] // 11000001-01010101-11010101-00001101
+// CHECK-INST: fdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x0d,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d50d <unknown>
+
+fdot za.s[w10, 5], {z8.h - z11.h}, z5.h[1] // 11000001-01010101-11010101-00001101
+// CHECK-INST: fdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x0d,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d50d <unknown>
+
+fdot za.s[w11, 7, vgx4], {z12.h - z15.h}, z8.h[3] // 11000001-01011000-11111101-10001111
+// CHECK-INST: fdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]
+// CHECK-ENCODING: [0x8f,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fd8f <unknown>
+
+fdot za.s[w11, 7], {z12.h - z15.h}, z8.h[3] // 11000001-01011000-11111101-10001111
+// CHECK-INST: fdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]
+// CHECK-ENCODING: [0x8f,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fd8f <unknown>
+
+fdot za.s[w11, 7, vgx4], {z28.h - z31.h}, z15.h[3] // 11000001-01011111-11111111-10001111
+// CHECK-INST: fdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]
+// CHECK-ENCODING: [0x8f,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fff8f <unknown>
+
+fdot za.s[w11, 7], {z28.h - z31.h}, z15.h[3] // 11000001-01011111-11111111-10001111
+// CHECK-INST: fdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]
+// CHECK-ENCODING: [0x8f,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fff8f <unknown>
+
+fdot za.s[w8, 5, vgx4], {z16.h - z19.h}, z0.h[3] // 11000001-01010000-10011110-00001101
+// CHECK-INST: fdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]
+// CHECK-ENCODING: [0x0d,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e0d <unknown>
+
+fdot za.s[w8, 5], {z16.h - z19.h}, z0.h[3] // 11000001-01010000-10011110-00001101
+// CHECK-INST: fdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]
+// CHECK-ENCODING: [0x0d,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e0d <unknown>
+
+fdot za.s[w8, 1, vgx4], {z0.h - z3.h}, z14.h[1] // 11000001-01011110-10010100-00001001
+// CHECK-INST: fdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x09,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9409 <unknown>
+
+fdot za.s[w8, 1], {z0.h - z3.h}, z14.h[1] // 11000001-01011110-10010100-00001001
+// CHECK-INST: fdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x09,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9409 <unknown>
+
+fdot za.s[w10, 0, vgx4], {z16.h - z19.h}, z4.h[1] // 11000001-01010100-11010110-00001000
+// CHECK-INST: fdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x08,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d608 <unknown>
+
+fdot za.s[w10, 0], {z16.h - z19.h}, z4.h[1] // 11000001-01010100-11010110-00001000
+// CHECK-INST: fdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x08,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d608 <unknown>
+
+fdot za.s[w8, 0, vgx4], {z12.h - z15.h}, z2.h[2] // 11000001-01010010-10011001-10001000
+// CHECK-INST: fdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]
+// CHECK-ENCODING: [0x88,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1529988 <unknown>
+
+fdot za.s[w8, 0], {z12.h - z15.h}, z2.h[2] // 11000001-01010010-10011001-10001000
+// CHECK-INST: fdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]
+// CHECK-ENCODING: [0x88,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1529988 <unknown>
+
+fdot za.s[w10, 1, vgx4], {z0.h - z3.h}, z10.h[2] // 11000001-01011010-11011000-00001001
+// CHECK-INST: fdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]
+// CHECK-ENCODING: [0x09,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad809 <unknown>
+
+fdot za.s[w10, 1], {z0.h - z3.h}, z10.h[2] // 11000001-01011010-11011000-00001001
+// CHECK-INST: fdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]
+// CHECK-ENCODING: [0x09,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad809 <unknown>
+
+fdot za.s[w8, 5, vgx4], {z20.h - z23.h}, z14.h[2] // 11000001-01011110-10011010-10001101
+// CHECK-INST: fdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]
+// CHECK-ENCODING: [0x8d,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9a8d <unknown>
+
+fdot za.s[w8, 5], {z20.h - z23.h}, z14.h[2] // 11000001-01011110-10011010-10001101
+// CHECK-INST: fdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]
+// CHECK-ENCODING: [0x8d,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9a8d <unknown>
+
+fdot za.s[w11, 2, vgx4], {z8.h - z11.h}, z1.h[1] // 11000001-01010001-11110101-00001010
+// CHECK-INST: fdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x0a,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f50a <unknown>
+
+fdot za.s[w11, 2], {z8.h - z11.h}, z1.h[1] // 11000001-01010001-11110101-00001010
+// CHECK-INST: fdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x0a,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f50a <unknown>
+
+fdot za.s[w9, 7, vgx4], {z12.h - z15.h}, z11.h[2] // 11000001-01011011-10111001-10001111
+// CHECK-INST: fdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]
+// CHECK-ENCODING: [0x8f,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb98f <unknown>
+
+fdot za.s[w9, 7], {z12.h - z15.h}, z11.h[2] // 11000001-01011011-10111001-10001111
+// CHECK-INST: fdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]
+// CHECK-ENCODING: [0x8f,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb98f <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/fmla.s b/llvm/test/MC/AArch64/SME2/fmla.s
index 1f46ad3a70b53..b7e35209edff8 100644
--- a/llvm/test/MC/AArch64/SME2/fmla.s
+++ b/llvm/test/MC/AArch64/SME2/fmla.s
@@ -157,6 +157,151 @@ fmla za.d[w9, 7], {z12.d - z13.d}, z11.d // 11000001-01101011-00111001-10000
// CHECK-UNKNOWN: c16b3987 <unknown>
+fmla za.d[w8, 0, vgx2], {z0.d, z1.d}, z0.d[0] // 11000001-11010000-00000000-00000000
+// CHECK-INST: fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d[0]
+// CHECK-ENCODING: [0x00,0x00,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d00000 <unknown>
+
+fmla za.d[w8, 0], {z0.d, z1.d}, z0.d[0] // 11000001-11010000-00000000-00000000
+// CHECK-INST: fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d[0]
+// CHECK-ENCODING: [0x00,0x00,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d00000 <unknown>
+
+fmla za.d[w10, 5, vgx2], {z10.d, z11.d}, z5.d[1] // 11000001-11010101-01000101-01000101
+// CHECK-INST: fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d[1]
+// CHECK-ENCODING: [0x45,0x45,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d54545 <unknown>
+
+fmla za.d[w10, 5], {z10.d, z11.d}, z5.d[1] // 11000001-11010101-01000101-01000101
+// CHECK-INST: fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d[1]
+// CHECK-ENCODING: [0x45,0x45,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d54545 <unknown>
+
+fmla za.d[w11, 7, vgx2], {z12.d, z13.d}, z8.d[1] // 11000001-11011000-01100101-10000111
+// CHECK-INST: fmla za.d[w11, 7, vgx2], { z12.d, z13.d }, z8.d[1]
+// CHECK-ENCODING: [0x87,0x65,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d86587 <unknown>
+
+fmla za.d[w11, 7], {z12.d, z13.d}, z8.d[1] // 11000001-11011000-01100101-10000111
+// CHECK-INST: fmla za.d[w11, 7, vgx2], { z12.d, z13.d }, z8.d[1]
+// CHECK-ENCODING: [0x87,0x65,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d86587 <unknown>
+
+fmla za.d[w11, 7, vgx2], {z30.d, z31.d}, z15.d[1] // 11000001-11011111-01100111-11000111
+// CHECK-INST: fmla za.d[w11, 7, vgx2], { z30.d, z31.d }, z15.d[1]
+// CHECK-ENCODING: [0xc7,0x67,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df67c7 <unknown>
+
+fmla za.d[w11, 7], {z30.d, z31.d}, z15.d[1] // 11000001-11011111-01100111-11000111
+// CHECK-INST: fmla za.d[w11, 7, vgx2], { z30.d, z31.d }, z15.d[1]
+// CHECK-ENCODING: [0xc7,0x67,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df67c7 <unknown>
+
+fmla za.d[w8, 5, vgx2], {z16.d, z17.d}, z0.d[1] // 11000001-11010000-00000110-00000101
+// CHECK-INST: fmla za.d[w8, 5, vgx2], { z16.d, z17.d }, z0.d[1]
+// CHECK-ENCODING: [0x05,0x06,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d00605 <unknown>
+
+fmla za.d[w8, 5], {z16.d, z17.d}, z0.d[1] // 11000001-11010000-00000110-00000101
+// CHECK-INST: fmla za.d[w8, 5, vgx2], { z16.d, z17.d }, z0.d[1]
+// CHECK-ENCODING: [0x05,0x06,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d00605 <unknown>
+
+fmla za.d[w8, 1, vgx2], {z0.d, z1.d}, z14.d[1] // 11000001-11011110-00000100-00000001
+// CHECK-INST: fmla za.d[w8, 1, vgx2], { z0.d, z1.d }, z14.d[1]
+// CHECK-ENCODING: [0x01,0x04,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de0401 <unknown>
+
+fmla za.d[w8, 1], {z0.d, z1.d}, z14.d[1] // 11000001-11011110-00000100-00000001
+// CHECK-INST: fmla za.d[w8, 1, vgx2], { z0.d, z1.d }, z14.d[1]
+// CHECK-ENCODING: [0x01,0x04,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de0401 <unknown>
+
+fmla za.d[w10, 0, vgx2], {z18.d, z19.d}, z4.d[1] // 11000001-11010100-01000110-01000000
+// CHECK-INST: fmla za.d[w10, 0, vgx2], { z18.d, z19.d }, z4.d[1]
+// CHECK-ENCODING: [0x40,0x46,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d44640 <unknown>
+
+fmla za.d[w10, 0], {z18.d, z19.d}, z4.d[1] // 11000001-11010100-01000110-01000000
+// CHECK-INST: fmla za.d[w10, 0, vgx2], { z18.d, z19.d }, z4.d[1]
+// CHECK-ENCODING: [0x40,0x46,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d44640 <unknown>
+
+fmla za.d[w8, 0, vgx2], {z12.d, z13.d}, z2.d[0] // 11000001-11010010-00000001-10000000
+// CHECK-INST: fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d[0]
+// CHECK-ENCODING: [0x80,0x01,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d20180 <unknown>
+
+fmla za.d[w8, 0], {z12.d, z13.d}, z2.d[0] // 11000001-11010010-00000001-10000000
+// CHECK-INST: fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d[0]
+// CHECK-ENCODING: [0x80,0x01,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d20180 <unknown>
+
+fmla za.d[w10, 1, vgx2], {z0.d, z1.d}, z10.d[0] // 11000001-11011010-01000000-00000001
+// CHECK-INST: fmla za.d[w10, 1, vgx2], { z0.d, z1.d }, z10.d[0]
+// CHECK-ENCODING: [0x01,0x40,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da4001 <unknown>
+
+fmla za.d[w10, 1], {z0.d, z1.d}, z10.d[0] // 11000001-11011010-01000000-00000001
+// CHECK-INST: fmla za.d[w10, 1, vgx2], { z0.d, z1.d }, z10.d[0]
+// CHECK-ENCODING: [0x01,0x40,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da4001 <unknown>
+
+fmla za.d[w8, 5, vgx2], {z22.d, z23.d}, z14.d[0] // 11000001-11011110-00000010-11000101
+// CHECK-INST: fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d[0]
+// CHECK-ENCODING: [0xc5,0x02,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de02c5 <unknown>
+
+fmla za.d[w8, 5], {z22.d, z23.d}, z14.d[0] // 11000001-11011110-00000010-11000101
+// CHECK-INST: fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d[0]
+// CHECK-ENCODING: [0xc5,0x02,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de02c5 <unknown>
+
+fmla za.d[w11, 2, vgx2], {z8.d, z9.d}, z1.d[1] // 11000001-11010001-01100101-00000010
+// CHECK-INST: fmla za.d[w11, 2, vgx2], { z8.d, z9.d }, z1.d[1]
+// CHECK-ENCODING: [0x02,0x65,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d16502 <unknown>
+
+fmla za.d[w11, 2], {z8.d, z9.d}, z1.d[1] // 11000001-11010001-01100101-00000010
+// CHECK-INST: fmla za.d[w11, 2, vgx2], { z8.d, z9.d }, z1.d[1]
+// CHECK-ENCODING: [0x02,0x65,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d16502 <unknown>
+
+fmla za.d[w9, 7, vgx2], {z12.d, z13.d}, z11.d[0] // 11000001-11011011-00100001-10000111
+// CHECK-INST: fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d[0]
+// CHECK-ENCODING: [0x87,0x21,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db2187 <unknown>
+
+fmla za.d[w9, 7], {z12.d, z13.d}, z11.d[0] // 11000001-11011011-00100001-10000111
+// CHECK-INST: fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d[0]
+// CHECK-ENCODING: [0x87,0x21,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db2187 <unknown>
+
+
fmla za.d[w8, 0, vgx2], {z0.d, z1.d}, {z0.d, z1.d} // 11000001, 11100000, 00011000, 00000000
// CHECK-INST: fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }
// CHECK-ENCODING: [0x00,0x18,0xe0,0xc1]
@@ -447,6 +592,151 @@ fmla za.s[w9, 7], {z12.s - z13.s}, z11.s // 11000001-00101011-00111001-10000
// CHECK-UNKNOWN: c12b3987 <unknown>
+fmla za.s[w8, 0, vgx2], {z0.s, z1.s}, z0.s[0] // 11000001-01010000-00000000-00000000
+// CHECK-INST: fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s[0]
+// CHECK-ENCODING: [0x00,0x00,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500000 <unknown>
+
+fmla za.s[w8, 0], {z0.s, z1.s}, z0.s[0] // 11000001-01010000-00000000-00000000
+// CHECK-INST: fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s[0]
+// CHECK-ENCODING: [0x00,0x00,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500000 <unknown>
+
+fmla za.s[w10, 5, vgx2], {z10.s, z11.s}, z5.s[1] // 11000001-01010101-01000101-01000101
+// CHECK-INST: fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s[1]
+// CHECK-ENCODING: [0x45,0x45,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1554545 <unknown>
+
+fmla za.s[w10, 5], {z10.s, z11.s}, z5.s[1] // 11000001-01010101-01000101-01000101
+// CHECK-INST: fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s[1]
+// CHECK-ENCODING: [0x45,0x45,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1554545 <unknown>
+
+fmla za.s[w11, 7, vgx2], {z12.s, z13.s}, z8.s[3] // 11000001-01011000-01101101-10000111
+// CHECK-INST: fmla za.s[w11, 7, vgx2], { z12.s, z13.s }, z8.s[3]
+// CHECK-ENCODING: [0x87,0x6d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1586d87 <unknown>
+
+fmla za.s[w11, 7], {z12.s, z13.s}, z8.s[3] // 11000001-01011000-01101101-10000111
+// CHECK-INST: fmla za.s[w11, 7, vgx2], { z12.s, z13.s }, z8.s[3]
+// CHECK-ENCODING: [0x87,0x6d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1586d87 <unknown>
+
+fmla za.s[w11, 7, vgx2], {z30.s, z31.s}, z15.s[3] // 11000001-01011111-01101111-11000111
+// CHECK-INST: fmla za.s[w11, 7, vgx2], { z30.s, z31.s }, z15.s[3]
+// CHECK-ENCODING: [0xc7,0x6f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f6fc7 <unknown>
+
+fmla za.s[w11, 7], {z30.s, z31.s}, z15.s[3] // 11000001-01011111-01101111-11000111
+// CHECK-INST: fmla za.s[w11, 7, vgx2], { z30.s, z31.s }, z15.s[3]
+// CHECK-ENCODING: [0xc7,0x6f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f6fc7 <unknown>
+
+fmla za.s[w8, 5, vgx2], {z16.s, z17.s}, z0.s[3] // 11000001-01010000-00001110-00000101
+// CHECK-INST: fmla za.s[w8, 5, vgx2], { z16.s, z17.s }, z0.s[3]
+// CHECK-ENCODING: [0x05,0x0e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500e05 <unknown>
+
+fmla za.s[w8, 5], {z16.s, z17.s}, z0.s[3] // 11000001-01010000-00001110-00000101
+// CHECK-INST: fmla za.s[w8, 5, vgx2], { z16.s, z17.s }, z0.s[3]
+// CHECK-ENCODING: [0x05,0x0e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500e05 <unknown>
+
+fmla za.s[w8, 1, vgx2], {z0.s, z1.s}, z14.s[1] // 11000001-01011110-00000100-00000001
+// CHECK-INST: fmla za.s[w8, 1, vgx2], { z0.s, z1.s }, z14.s[1]
+// CHECK-ENCODING: [0x01,0x04,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0401 <unknown>
+
+fmla za.s[w8, 1], {z0.s, z1.s}, z14.s[1] // 11000001-01011110-00000100-00000001
+// CHECK-INST: fmla za.s[w8, 1, vgx2], { z0.s, z1.s }, z14.s[1]
+// CHECK-ENCODING: [0x01,0x04,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0401 <unknown>
+
+fmla za.s[w10, 0, vgx2], {z18.s, z19.s}, z4.s[1] // 11000001-01010100-01000110-01000000
+// CHECK-INST: fmla za.s[w10, 0, vgx2], { z18.s, z19.s }, z4.s[1]
+// CHECK-ENCODING: [0x40,0x46,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1544640 <unknown>
+
+fmla za.s[w10, 0], {z18.s, z19.s}, z4.s[1] // 11000001-01010100-01000110-01000000
+// CHECK-INST: fmla za.s[w10, 0, vgx2], { z18.s, z19.s }, z4.s[1]
+// CHECK-ENCODING: [0x40,0x46,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1544640 <unknown>
+
+fmla za.s[w8, 0, vgx2], {z12.s, z13.s}, z2.s[2] // 11000001-01010010-00001001-10000000
+// CHECK-INST: fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s[2]
+// CHECK-ENCODING: [0x80,0x09,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1520980 <unknown>
+
+fmla za.s[w8, 0], {z12.s, z13.s}, z2.s[2] // 11000001-01010010-00001001-10000000
+// CHECK-INST: fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s[2]
+// CHECK-ENCODING: [0x80,0x09,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1520980 <unknown>
+
+fmla za.s[w10, 1, vgx2], {z0.s, z1.s}, z10.s[2] // 11000001-01011010-01001000-00000001
+// CHECK-INST: fmla za.s[w10, 1, vgx2], { z0.s, z1.s }, z10.s[2]
+// CHECK-ENCODING: [0x01,0x48,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a4801 <unknown>
+
+fmla za.s[w10, 1], {z0.s, z1.s}, z10.s[2] // 11000001-01011010-01001000-00000001
+// CHECK-INST: fmla za.s[w10, 1, vgx2], { z0.s, z1.s }, z10.s[2]
+// CHECK-ENCODING: [0x01,0x48,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a4801 <unknown>
+
+fmla za.s[w8, 5, vgx2], {z22.s, z23.s}, z14.s[2] // 11000001-01011110-00001010-11000101
+// CHECK-INST: fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s[2]
+// CHECK-ENCODING: [0xc5,0x0a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0ac5 <unknown>
+
+fmla za.s[w8, 5], {z22.s, z23.s}, z14.s[2] // 11000001-01011110-00001010-11000101
+// CHECK-INST: fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s[2]
+// CHECK-ENCODING: [0xc5,0x0a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0ac5 <unknown>
+
+fmla za.s[w11, 2, vgx2], {z8.s, z9.s}, z1.s[1] // 11000001-01010001-01100101-00000010
+// CHECK-INST: fmla za.s[w11, 2, vgx2], { z8.s, z9.s }, z1.s[1]
+// CHECK-ENCODING: [0x02,0x65,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1516502 <unknown>
+
+fmla za.s[w11, 2], {z8.s, z9.s}, z1.s[1] // 11000001-01010001-01100101-00000010
+// CHECK-INST: fmla za.s[w11, 2, vgx2], { z8.s, z9.s }, z1.s[1]
+// CHECK-ENCODING: [0x02,0x65,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1516502 <unknown>
+
+fmla za.s[w9, 7, vgx2], {z12.s, z13.s}, z11.s[2] // 11000001-01011011-00101001-10000111
+// CHECK-INST: fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s[2]
+// CHECK-ENCODING: [0x87,0x29,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b2987 <unknown>
+
+fmla za.s[w9, 7], {z12.s, z13.s}, z11.s[2] // 11000001-01011011-00101001-10000111
+// CHECK-INST: fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s[2]
+// CHECK-ENCODING: [0x87,0x29,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b2987 <unknown>
+
+
fmla za.s[w8, 0, vgx2], {z0.s, z1.s}, {z0.s, z1.s} // 11000001, 10100000, 00011000, 00000000
// CHECK-INST: fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }
// CHECK-ENCODING: [0x00,0x18,0xa0,0xc1]
@@ -737,6 +1027,151 @@ fmla za.d[w9, 7], {z12.d - z15.d}, z11.d // 11000001-01111011-00111001-10000
// CHECK-UNKNOWN: c17b3987 <unknown>
+fmla za.d[w8, 0, vgx4], {z0.d - z3.d}, z0.d[0] // 11000001-11010000-10000000-00000000
+// CHECK-INST: fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]
+// CHECK-ENCODING: [0x00,0x80,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08000 <unknown>
+
+fmla za.d[w8, 0], {z0.d - z3.d}, z0.d[0] // 11000001-11010000-10000000-00000000
+// CHECK-INST: fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]
+// CHECK-ENCODING: [0x00,0x80,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08000 <unknown>
+
+fmla za.d[w10, 5, vgx4], {z8.d - z11.d}, z5.d[1] // 11000001-11010101-11000101-00000101
+// CHECK-INST: fmla za.d[w10, 5, vgx4], { z8.d - z11.d }, z5.d[1]
+// CHECK-ENCODING: [0x05,0xc5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5c505 <unknown>
+
+fmla za.d[w10, 5], {z8.d - z11.d}, z5.d[1] // 11000001-11010101-11000101-00000101
+// CHECK-INST: fmla za.d[w10, 5, vgx4], { z8.d - z11.d }, z5.d[1]
+// CHECK-ENCODING: [0x05,0xc5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5c505 <unknown>
+
+fmla za.d[w11, 7, vgx4], {z12.d - z15.d}, z8.d[1] // 11000001-11011000-11100101-10000111
+// CHECK-INST: fmla za.d[w11, 7, vgx4], { z12.d - z15.d }, z8.d[1]
+// CHECK-ENCODING: [0x87,0xe5,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8e587 <unknown>
+
+fmla za.d[w11, 7], {z12.d - z15.d}, z8.d[1] // 11000001-11011000-11100101-10000111
+// CHECK-INST: fmla za.d[w11, 7, vgx4], { z12.d - z15.d }, z8.d[1]
+// CHECK-ENCODING: [0x87,0xe5,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8e587 <unknown>
+
+fmla za.d[w11, 7, vgx4], {z28.d - z31.d}, z15.d[1] // 11000001-11011111-11100111-10000111
+// CHECK-INST: fmla za.d[w11, 7, vgx4], { z28.d - z31.d }, z15.d[1]
+// CHECK-ENCODING: [0x87,0xe7,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfe787 <unknown>
+
+fmla za.d[w11, 7], {z28.d - z31.d}, z15.d[1] // 11000001-11011111-11100111-10000111
+// CHECK-INST: fmla za.d[w11, 7, vgx4], { z28.d - z31.d }, z15.d[1]
+// CHECK-ENCODING: [0x87,0xe7,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfe787 <unknown>
+
+fmla za.d[w8, 5, vgx4], {z16.d - z19.d}, z0.d[1] // 11000001-11010000-10000110-00000101
+// CHECK-INST: fmla za.d[w8, 5, vgx4], { z16.d - z19.d }, z0.d[1]
+// CHECK-ENCODING: [0x05,0x86,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08605 <unknown>
+
+fmla za.d[w8, 5], {z16.d - z19.d}, z0.d[1] // 11000001-11010000-10000110-00000101
+// CHECK-INST: fmla za.d[w8, 5, vgx4], { z16.d - z19.d }, z0.d[1]
+// CHECK-ENCODING: [0x05,0x86,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08605 <unknown>
+
+fmla za.d[w8, 1, vgx4], {z0.d - z3.d}, z14.d[1] // 11000001-11011110-10000100-00000001
+// CHECK-INST: fmla za.d[w8, 1, vgx4], { z0.d - z3.d }, z14.d[1]
+// CHECK-ENCODING: [0x01,0x84,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8401 <unknown>
+
+fmla za.d[w8, 1], {z0.d - z3.d}, z14.d[1] // 11000001-11011110-10000100-00000001
+// CHECK-INST: fmla za.d[w8, 1, vgx4], { z0.d - z3.d }, z14.d[1]
+// CHECK-ENCODING: [0x01,0x84,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8401 <unknown>
+
+fmla za.d[w10, 0, vgx4], {z16.d - z19.d}, z4.d[1] // 11000001-11010100-11000110-00000000
+// CHECK-INST: fmla za.d[w10, 0, vgx4], { z16.d - z19.d }, z4.d[1]
+// CHECK-ENCODING: [0x00,0xc6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4c600 <unknown>
+
+fmla za.d[w10, 0], {z16.d - z19.d}, z4.d[1] // 11000001-11010100-11000110-00000000
+// CHECK-INST: fmla za.d[w10, 0, vgx4], { z16.d - z19.d }, z4.d[1]
+// CHECK-ENCODING: [0x00,0xc6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4c600 <unknown>
+
+fmla za.d[w8, 0, vgx4], {z12.d - z15.d}, z2.d[0] // 11000001-11010010-10000001-10000000
+// CHECK-INST: fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d[0]
+// CHECK-ENCODING: [0x80,0x81,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d28180 <unknown>
+
+fmla za.d[w8, 0], {z12.d - z15.d}, z2.d[0] // 11000001-11010010-10000001-10000000
+// CHECK-INST: fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d[0]
+// CHECK-ENCODING: [0x80,0x81,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d28180 <unknown>
+
+fmla za.d[w10, 1, vgx4], {z0.d - z3.d}, z10.d[0] // 11000001-11011010-11000000-00000001
+// CHECK-INST: fmla za.d[w10, 1, vgx4], { z0.d - z3.d }, z10.d[0]
+// CHECK-ENCODING: [0x01,0xc0,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dac001 <unknown>
+
+fmla za.d[w10, 1], {z0.d - z3.d}, z10.d[0] // 11000001-11011010-11000000-00000001
+// CHECK-INST: fmla za.d[w10, 1, vgx4], { z0.d - z3.d }, z10.d[0]
+// CHECK-ENCODING: [0x01,0xc0,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dac001 <unknown>
+
+fmla za.d[w8, 5, vgx4], {z20.d - z23.d}, z14.d[0] // 11000001-11011110-10000010-10000101
+// CHECK-INST: fmla za.d[w8, 5, vgx4], { z20.d - z23.d }, z14.d[0]
+// CHECK-ENCODING: [0x85,0x82,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8285 <unknown>
+
+fmla za.d[w8, 5], {z20.d - z23.d}, z14.d[0] // 11000001-11011110-10000010-10000101
+// CHECK-INST: fmla za.d[w8, 5, vgx4], { z20.d - z23.d }, z14.d[0]
+// CHECK-ENCODING: [0x85,0x82,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8285 <unknown>
+
+fmla za.d[w11, 2, vgx4], {z8.d - z11.d}, z1.d[1] // 11000001-11010001-11100101-00000010
+// CHECK-INST: fmla za.d[w11, 2, vgx4], { z8.d - z11.d }, z1.d[1]
+// CHECK-ENCODING: [0x02,0xe5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1e502 <unknown>
+
+fmla za.d[w11, 2], {z8.d - z11.d}, z1.d[1] // 11000001-11010001-11100101-00000010
+// CHECK-INST: fmla za.d[w11, 2, vgx4], { z8.d - z11.d }, z1.d[1]
+// CHECK-ENCODING: [0x02,0xe5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1e502 <unknown>
+
+fmla za.d[w9, 7, vgx4], {z12.d - z15.d}, z11.d[0] // 11000001-11011011-10100001-10000111
+// CHECK-INST: fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d[0]
+// CHECK-ENCODING: [0x87,0xa1,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dba187 <unknown>
+
+fmla za.d[w9, 7], {z12.d - z15.d}, z11.d[0] // 11000001-11011011-10100001-10000111
+// CHECK-INST: fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d[0]
+// CHECK-ENCODING: [0x87,0xa1,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dba187 <unknown>
+
+
fmla za.d[w8, 0, vgx4], {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100001-00011000-00000000
// CHECK-INST: fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
// CHECK-ENCODING: [0x00,0x18,0xe1,0xc1]
@@ -1027,6 +1462,150 @@ fmla za.s[w9, 7], {z12.s - z15.s}, z11.s // 11000001-00111011-00111001-10000
// CHECK-UNKNOWN: c13b3987 <unknown>
+fmla za.s[w8, 0, vgx4], {z0.s - z3.s}, z0.s[0] // 11000001-01010000-10000000-00000000
+// CHECK-INST: fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]
+// CHECK-ENCODING: [0x00,0x80,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508000 <unknown>
+
+fmla za.s[w8, 0], {z0.s - z3.s}, z0.s[0] // 11000001-01010000-10000000-00000000
+// CHECK-INST: fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]
+// CHECK-ENCODING: [0x00,0x80,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508000 <unknown>
+
+fmla za.s[w10, 5, vgx4], {z8.s - z11.s}, z5.s[1] // 11000001-01010101-11000101-00000101
+// CHECK-INST: fmla za.s[w10, 5, vgx4], { z8.s - z11.s }, z5.s[1]
+// CHECK-ENCODING: [0x05,0xc5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155c505 <unknown>
+
+fmla za.s[w10, 5], {z8.s - z11.s}, z5.s[1] // 11000001-01010101-11000101-00000101
+// CHECK-INST: fmla za.s[w10, 5, vgx4], { z8.s - z11.s }, z5.s[1]
+// CHECK-ENCODING: [0x05,0xc5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155c505 <unknown>
+
+fmla za.s[w11, 7, vgx4], {z12.s - z15.s}, z8.s[3] // 11000001-01011000-11101101-10000111
+// CHECK-INST: fmla za.s[w11, 7, vgx4], { z12.s - z15.s }, z8.s[3]
+// CHECK-ENCODING: [0x87,0xed,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158ed87 <unknown>
+
+fmla za.s[w11, 7], {z12.s - z15.s}, z8.s[3] // 11000001-01011000-11101101-10000111
+// CHECK-INST: fmla za.s[w11, 7, vgx4], { z12.s - z15.s }, z8.s[3]
+// CHECK-ENCODING: [0x87,0xed,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158ed87 <unknown>
+
+fmla za.s[w11, 7, vgx4], {z28.s - z31.s}, z15.s[3] // 11000001-01011111-11101111-10000111
+// CHECK-INST: fmla za.s[w11, 7, vgx4], { z28.s - z31.s }, z15.s[3]
+// CHECK-ENCODING: [0x87,0xef,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fef87 <unknown>
+
+fmla za.s[w11, 7], {z28.s - z31.s}, z15.s[3] // 11000001-01011111-11101111-10000111
+// CHECK-INST: fmla za.s[w11, 7, vgx4], { z28.s - z31.s }, z15.s[3]
+// CHECK-ENCODING: [0x87,0xef,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fef87 <unknown>
+
+fmla za.s[w8, 5, vgx4], {z16.s - z19.s}, z0.s[3] // 11000001-01010000-10001110-00000101
+// CHECK-INST: fmla za.s[w8, 5, vgx4], { z16.s - z19.s }, z0.s[3]
+// CHECK-ENCODING: [0x05,0x8e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508e05 <unknown>
+
+fmla za.s[w8, 5], {z16.s - z19.s}, z0.s[3] // 11000001-01010000-10001110-00000101
+// CHECK-INST: fmla za.s[w8, 5, vgx4], { z16.s - z19.s }, z0.s[3]
+// CHECK-ENCODING: [0x05,0x8e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508e05 <unknown>
+
+fmla za.s[w8, 1, vgx4], {z0.s - z3.s}, z14.s[1] // 11000001-01011110-10000100-00000001
+// CHECK-INST: fmla za.s[w8, 1, vgx4], { z0.s - z3.s }, z14.s[1]
+// CHECK-ENCODING: [0x01,0x84,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8401 <unknown>
+
+fmla za.s[w8, 1], {z0.s - z3.s}, z14.s[1] // 11000001-01011110-10000100-00000001
+// CHECK-INST: fmla za.s[w8, 1, vgx4], { z0.s - z3.s }, z14.s[1]
+// CHECK-ENCODING: [0x01,0x84,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8401 <unknown>
+
+fmla za.s[w10, 0, vgx4], {z16.s - z19.s}, z4.s[1] // 11000001-01010100-11000110-00000000
+// CHECK-INST: fmla za.s[w10, 0, vgx4], { z16.s - z19.s }, z4.s[1]
+// CHECK-ENCODING: [0x00,0xc6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154c600 <unknown>
+
+fmla za.s[w10, 0], {z16.s - z19.s}, z4.s[1] // 11000001-01010100-11000110-00000000
+// CHECK-INST: fmla za.s[w10, 0, vgx4], { z16.s - z19.s }, z4.s[1]
+// CHECK-ENCODING: [0x00,0xc6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154c600 <unknown>
+
+fmla za.s[w8, 0, vgx4], {z12.s - z15.s}, z2.s[2] // 11000001-01010010-10001001-10000000
+// CHECK-INST: fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s[2]
+// CHECK-ENCODING: [0x80,0x89,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1528980 <unknown>
+
+fmla za.s[w8, 0], {z12.s - z15.s}, z2.s[2] // 11000001-01010010-10001001-10000000
+// CHECK-INST: fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s[2]
+// CHECK-ENCODING: [0x80,0x89,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1528980 <unknown>
+
+fmla za.s[w10, 1, vgx4], {z0.s - z3.s}, z10.s[2] // 11000001-01011010-11001000-00000001
+// CHECK-INST: fmla za.s[w10, 1, vgx4], { z0.s - z3.s }, z10.s[2]
+// CHECK-ENCODING: [0x01,0xc8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ac801 <unknown>
+
+fmla za.s[w10, 1], {z0.s - z3.s}, z10.s[2] // 11000001-01011010-11001000-00000001
+// CHECK-INST: fmla za.s[w10, 1, vgx4], { z0.s - z3.s }, z10.s[2]
+// CHECK-ENCODING: [0x01,0xc8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ac801 <unknown>
+
+fmla za.s[w8, 5, vgx4], {z20.s - z23.s}, z14.s[2] // 11000001-01011110-10001010-10000101
+// CHECK-INST: fmla za.s[w8, 5, vgx4], { z20.s - z23.s }, z14.s[2]
+// CHECK-ENCODING: [0x85,0x8a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8a85 <unknown>
+
+fmla za.s[w8, 5], {z20.s - z23.s}, z14.s[2] // 11000001-01011110-10001010-10000101
+// CHECK-INST: fmla za.s[w8, 5, vgx4], { z20.s - z23.s }, z14.s[2]
+// CHECK-ENCODING: [0x85,0x8a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8a85 <unknown>
+
+fmla za.s[w11, 2, vgx4], {z8.s - z11.s}, z1.s[1] // 11000001-01010001-11100101-00000010
+// CHECK-INST: fmla za.s[w11, 2, vgx4], { z8.s - z11.s }, z1.s[1]
+// CHECK-ENCODING: [0x02,0xe5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151e502 <unknown>
+
+fmla za.s[w11, 2], {z8.s - z11.s}, z1.s[1] // 11000001-01010001-11100101-00000010
+// CHECK-INST: fmla za.s[w11, 2, vgx4], { z8.s - z11.s }, z1.s[1]
+// CHECK-ENCODING: [0x02,0xe5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151e502 <unknown>
+
+fmla za.s[w9, 7, vgx4], {z12.s - z15.s}, z11.s[2] // 11000001-01011011-10101001-10000111
+// CHECK-INST: fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s[2]
+// CHECK-ENCODING: [0x87,0xa9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ba987 <unknown>
+
+fmla za.s[w9, 7], {z12.s - z15.s}, z11.s[2] // 11000001-01011011-10101001-10000111
+// CHECK-INST: fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s[2]
+// CHECK-ENCODING: [0x87,0xa9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ba987 <unknown>
+
fmla za.s[w8, 0, vgx4], {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100001-00011000-00000000
// CHECK-INST: fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
diff --git a/llvm/test/MC/AArch64/SME2/fmls.s b/llvm/test/MC/AArch64/SME2/fmls.s
index be9874c36c9e8..7f58d04f4e756 100644
--- a/llvm/test/MC/AArch64/SME2/fmls.s
+++ b/llvm/test/MC/AArch64/SME2/fmls.s
@@ -157,7 +157,152 @@ fmls za.d[w9, 7], {z12.d - z13.d}, z11.d // 11000001-01101011-00111001-10001
// CHECK-UNKNOWN: c16b398f <unknown>
-fmls za.d[w8, 0, vgx2], {z0.d, z1.d}, {z0.d, z1.d} // 11000001, 11100000, 00011000, 00001000
+fmls za.d[w8, 0, vgx2], {z0.d, z1.d}, z0.d[0] // 11000001-11010000-00000000-00010000
+// CHECK-INST: fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d[0]
+// CHECK-ENCODING: [0x10,0x00,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d00010 <unknown>
+
+fmls za.d[w8, 0], {z0.d, z1.d}, z0.d[0] // 11000001-11010000-00000000-00010000
+// CHECK-INST: fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d[0]
+// CHECK-ENCODING: [0x10,0x00,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d00010 <unknown>
+
+fmls za.d[w10, 5, vgx2], {z10.d, z11.d}, z5.d[1] // 11000001-11010101-01000101-01010101
+// CHECK-INST: fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d[1]
+// CHECK-ENCODING: [0x55,0x45,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d54555 <unknown>
+
+fmls za.d[w10, 5], {z10.d, z11.d}, z5.d[1] // 11000001-11010101-01000101-01010101
+// CHECK-INST: fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d[1]
+// CHECK-ENCODING: [0x55,0x45,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d54555 <unknown>
+
+fmls za.d[w11, 7, vgx2], {z12.d, z13.d}, z8.d[1] // 11000001-11011000-01100101-10010111
+// CHECK-INST: fmls za.d[w11, 7, vgx2], { z12.d, z13.d }, z8.d[1]
+// CHECK-ENCODING: [0x97,0x65,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d86597 <unknown>
+
+fmls za.d[w11, 7], {z12.d, z13.d}, z8.d[1] // 11000001-11011000-01100101-10010111
+// CHECK-INST: fmls za.d[w11, 7, vgx2], { z12.d, z13.d }, z8.d[1]
+// CHECK-ENCODING: [0x97,0x65,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d86597 <unknown>
+
+fmls za.d[w11, 7, vgx2], {z30.d, z31.d}, z15.d[1] // 11000001-11011111-01100111-11010111
+// CHECK-INST: fmls za.d[w11, 7, vgx2], { z30.d, z31.d }, z15.d[1]
+// CHECK-ENCODING: [0xd7,0x67,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df67d7 <unknown>
+
+fmls za.d[w11, 7], {z30.d, z31.d}, z15.d[1] // 11000001-11011111-01100111-11010111
+// CHECK-INST: fmls za.d[w11, 7, vgx2], { z30.d, z31.d }, z15.d[1]
+// CHECK-ENCODING: [0xd7,0x67,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df67d7 <unknown>
+
+fmls za.d[w8, 5, vgx2], {z16.d, z17.d}, z0.d[1] // 11000001-11010000-00000110-00010101
+// CHECK-INST: fmls za.d[w8, 5, vgx2], { z16.d, z17.d }, z0.d[1]
+// CHECK-ENCODING: [0x15,0x06,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d00615 <unknown>
+
+fmls za.d[w8, 5], {z16.d, z17.d}, z0.d[1] // 11000001-11010000-00000110-00010101
+// CHECK-INST: fmls za.d[w8, 5, vgx2], { z16.d, z17.d }, z0.d[1]
+// CHECK-ENCODING: [0x15,0x06,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d00615 <unknown>
+
+fmls za.d[w8, 1, vgx2], {z0.d, z1.d}, z14.d[1] // 11000001-11011110-00000100-00010001
+// CHECK-INST: fmls za.d[w8, 1, vgx2], { z0.d, z1.d }, z14.d[1]
+// CHECK-ENCODING: [0x11,0x04,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de0411 <unknown>
+
+fmls za.d[w8, 1], {z0.d, z1.d}, z14.d[1] // 11000001-11011110-00000100-00010001
+// CHECK-INST: fmls za.d[w8, 1, vgx2], { z0.d, z1.d }, z14.d[1]
+// CHECK-ENCODING: [0x11,0x04,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de0411 <unknown>
+
+fmls za.d[w10, 0, vgx2], {z18.d, z19.d}, z4.d[1] // 11000001-11010100-01000110-01010000
+// CHECK-INST: fmls za.d[w10, 0, vgx2], { z18.d, z19.d }, z4.d[1]
+// CHECK-ENCODING: [0x50,0x46,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d44650 <unknown>
+
+fmls za.d[w10, 0], {z18.d, z19.d}, z4.d[1] // 11000001-11010100-01000110-01010000
+// CHECK-INST: fmls za.d[w10, 0, vgx2], { z18.d, z19.d }, z4.d[1]
+// CHECK-ENCODING: [0x50,0x46,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d44650 <unknown>
+
+fmls za.d[w8, 0, vgx2], {z12.d, z13.d}, z2.d[0] // 11000001-11010010-00000001-10010000
+// CHECK-INST: fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d[0]
+// CHECK-ENCODING: [0x90,0x01,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d20190 <unknown>
+
+fmls za.d[w8, 0], {z12.d, z13.d}, z2.d[0] // 11000001-11010010-00000001-10010000
+// CHECK-INST: fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d[0]
+// CHECK-ENCODING: [0x90,0x01,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d20190 <unknown>
+
+fmls za.d[w10, 1, vgx2], {z0.d, z1.d}, z10.d[0] // 11000001-11011010-01000000-00010001
+// CHECK-INST: fmls za.d[w10, 1, vgx2], { z0.d, z1.d }, z10.d[0]
+// CHECK-ENCODING: [0x11,0x40,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da4011 <unknown>
+
+fmls za.d[w10, 1], {z0.d, z1.d}, z10.d[0] // 11000001-11011010-01000000-00010001
+// CHECK-INST: fmls za.d[w10, 1, vgx2], { z0.d, z1.d }, z10.d[0]
+// CHECK-ENCODING: [0x11,0x40,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da4011 <unknown>
+
+fmls za.d[w8, 5, vgx2], {z22.d, z23.d}, z14.d[0] // 11000001-11011110-00000010-11010101
+// CHECK-INST: fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d[0]
+// CHECK-ENCODING: [0xd5,0x02,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de02d5 <unknown>
+
+fmls za.d[w8, 5], {z22.d, z23.d}, z14.d[0] // 11000001-11011110-00000010-11010101
+// CHECK-INST: fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d[0]
+// CHECK-ENCODING: [0xd5,0x02,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de02d5 <unknown>
+
+fmls za.d[w11, 2, vgx2], {z8.d, z9.d}, z1.d[1] // 11000001-11010001-01100101-00010010
+// CHECK-INST: fmls za.d[w11, 2, vgx2], { z8.d, z9.d }, z1.d[1]
+// CHECK-ENCODING: [0x12,0x65,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d16512 <unknown>
+
+fmls za.d[w11, 2], {z8.d, z9.d}, z1.d[1] // 11000001-11010001-01100101-00010010
+// CHECK-INST: fmls za.d[w11, 2, vgx2], { z8.d, z9.d }, z1.d[1]
+// CHECK-ENCODING: [0x12,0x65,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d16512 <unknown>
+
+fmls za.d[w9, 7, vgx2], {z12.d, z13.d}, z11.d[0] // 11000001-11011011-00100001-10010111
+// CHECK-INST: fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d[0]
+// CHECK-ENCODING: [0x97,0x21,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db2197 <unknown>
+
+fmls za.d[w9, 7], {z12.d, z13.d}, z11.d[0] // 11000001-11011011-00100001-10010111
+// CHECK-INST: fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d[0]
+// CHECK-ENCODING: [0x97,0x21,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db2197 <unknown>
+
+
+fmls za.d[w8, 0, vgx2], {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-00011000-00001000
// CHECK-INST: fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }
// CHECK-ENCODING: [0x08,0x18,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
@@ -447,7 +592,152 @@ fmls za.s[w9, 7], {z12.s - z13.s}, z11.s // 11000001-00101011-00111001-10001
// CHECK-UNKNOWN: c12b398f <unknown>
-fmls za.s[w8, 0, vgx2], {z0.s, z1.s}, {z0.s, z1.s} // 11000001, 10100000, 00011000, 00001000
+fmls za.s[w8, 0, vgx2], {z0.s, z1.s}, z0.s[0] // 11000001-01010000-00000000-00010000
+// CHECK-INST: fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s[0]
+// CHECK-ENCODING: [0x10,0x00,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500010 <unknown>
+
+fmls za.s[w8, 0], {z0.s, z1.s}, z0.s[0] // 11000001-01010000-00000000-00010000
+// CHECK-INST: fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s[0]
+// CHECK-ENCODING: [0x10,0x00,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500010 <unknown>
+
+fmls za.s[w10, 5, vgx2], {z10.s, z11.s}, z5.s[1] // 11000001-01010101-01000101-01010101
+// CHECK-INST: fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s[1]
+// CHECK-ENCODING: [0x55,0x45,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1554555 <unknown>
+
+fmls za.s[w10, 5], {z10.s, z11.s}, z5.s[1] // 11000001-01010101-01000101-01010101
+// CHECK-INST: fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s[1]
+// CHECK-ENCODING: [0x55,0x45,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1554555 <unknown>
+
+fmls za.s[w11, 7, vgx2], {z12.s, z13.s}, z8.s[3] // 11000001-01011000-01101101-10010111
+// CHECK-INST: fmls za.s[w11, 7, vgx2], { z12.s, z13.s }, z8.s[3]
+// CHECK-ENCODING: [0x97,0x6d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1586d97 <unknown>
+
+fmls za.s[w11, 7], {z12.s, z13.s}, z8.s[3] // 11000001-01011000-01101101-10010111
+// CHECK-INST: fmls za.s[w11, 7, vgx2], { z12.s, z13.s }, z8.s[3]
+// CHECK-ENCODING: [0x97,0x6d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1586d97 <unknown>
+
+fmls za.s[w11, 7, vgx2], {z30.s, z31.s}, z15.s[3] // 11000001-01011111-01101111-11010111
+// CHECK-INST: fmls za.s[w11, 7, vgx2], { z30.s, z31.s }, z15.s[3]
+// CHECK-ENCODING: [0xd7,0x6f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f6fd7 <unknown>
+
+fmls za.s[w11, 7], {z30.s, z31.s}, z15.s[3] // 11000001-01011111-01101111-11010111
+// CHECK-INST: fmls za.s[w11, 7, vgx2], { z30.s, z31.s }, z15.s[3]
+// CHECK-ENCODING: [0xd7,0x6f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f6fd7 <unknown>
+
+fmls za.s[w8, 5, vgx2], {z16.s, z17.s}, z0.s[3] // 11000001-01010000-00001110-00010101
+// CHECK-INST: fmls za.s[w8, 5, vgx2], { z16.s, z17.s }, z0.s[3]
+// CHECK-ENCODING: [0x15,0x0e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500e15 <unknown>
+
+fmls za.s[w8, 5], {z16.s, z17.s}, z0.s[3] // 11000001-01010000-00001110-00010101
+// CHECK-INST: fmls za.s[w8, 5, vgx2], { z16.s, z17.s }, z0.s[3]
+// CHECK-ENCODING: [0x15,0x0e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500e15 <unknown>
+
+fmls za.s[w8, 1, vgx2], {z0.s, z1.s}, z14.s[1] // 11000001-01011110-00000100-00010001
+// CHECK-INST: fmls za.s[w8, 1, vgx2], { z0.s, z1.s }, z14.s[1]
+// CHECK-ENCODING: [0x11,0x04,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0411 <unknown>
+
+fmls za.s[w8, 1], {z0.s, z1.s}, z14.s[1] // 11000001-01011110-00000100-00010001
+// CHECK-INST: fmls za.s[w8, 1, vgx2], { z0.s, z1.s }, z14.s[1]
+// CHECK-ENCODING: [0x11,0x04,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0411 <unknown>
+
+fmls za.s[w10, 0, vgx2], {z18.s, z19.s}, z4.s[1] // 11000001-01010100-01000110-01010000
+// CHECK-INST: fmls za.s[w10, 0, vgx2], { z18.s, z19.s }, z4.s[1]
+// CHECK-ENCODING: [0x50,0x46,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1544650 <unknown>
+
+fmls za.s[w10, 0], {z18.s, z19.s}, z4.s[1] // 11000001-01010100-01000110-01010000
+// CHECK-INST: fmls za.s[w10, 0, vgx2], { z18.s, z19.s }, z4.s[1]
+// CHECK-ENCODING: [0x50,0x46,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1544650 <unknown>
+
+fmls za.s[w8, 0, vgx2], {z12.s, z13.s}, z2.s[2] // 11000001-01010010-00001001-10010000
+// CHECK-INST: fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s[2]
+// CHECK-ENCODING: [0x90,0x09,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1520990 <unknown>
+
+fmls za.s[w8, 0], {z12.s, z13.s}, z2.s[2] // 11000001-01010010-00001001-10010000
+// CHECK-INST: fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s[2]
+// CHECK-ENCODING: [0x90,0x09,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1520990 <unknown>
+
+fmls za.s[w10, 1, vgx2], {z0.s, z1.s}, z10.s[2] // 11000001-01011010-01001000-00010001
+// CHECK-INST: fmls za.s[w10, 1, vgx2], { z0.s, z1.s }, z10.s[2]
+// CHECK-ENCODING: [0x11,0x48,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a4811 <unknown>
+
+fmls za.s[w10, 1], {z0.s, z1.s}, z10.s[2] // 11000001-01011010-01001000-00010001
+// CHECK-INST: fmls za.s[w10, 1, vgx2], { z0.s, z1.s }, z10.s[2]
+// CHECK-ENCODING: [0x11,0x48,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a4811 <unknown>
+
+fmls za.s[w8, 5, vgx2], {z22.s, z23.s}, z14.s[2] // 11000001-01011110-00001010-11010101
+// CHECK-INST: fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s[2]
+// CHECK-ENCODING: [0xd5,0x0a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0ad5 <unknown>
+
+fmls za.s[w8, 5], {z22.s, z23.s}, z14.s[2] // 11000001-01011110-00001010-11010101
+// CHECK-INST: fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s[2]
+// CHECK-ENCODING: [0xd5,0x0a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0ad5 <unknown>
+
+fmls za.s[w11, 2, vgx2], {z8.s, z9.s}, z1.s[1] // 11000001-01010001-01100101-00010010
+// CHECK-INST: fmls za.s[w11, 2, vgx2], { z8.s, z9.s }, z1.s[1]
+// CHECK-ENCODING: [0x12,0x65,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1516512 <unknown>
+
+fmls za.s[w11, 2], {z8.s, z9.s}, z1.s[1] // 11000001-01010001-01100101-00010010
+// CHECK-INST: fmls za.s[w11, 2, vgx2], { z8.s, z9.s }, z1.s[1]
+// CHECK-ENCODING: [0x12,0x65,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1516512 <unknown>
+
+fmls za.s[w9, 7, vgx2], {z12.s, z13.s}, z11.s[2] // 11000001-01011011-00101001-10010111
+// CHECK-INST: fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s[2]
+// CHECK-ENCODING: [0x97,0x29,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b2997 <unknown>
+
+fmls za.s[w9, 7], {z12.s, z13.s}, z11.s[2] // 11000001-01011011-00101001-10010111
+// CHECK-INST: fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s[2]
+// CHECK-ENCODING: [0x97,0x29,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b2997 <unknown>
+
+
+fmls za.s[w8, 0, vgx2], {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-00011000-00001000
// CHECK-INST: fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }
// CHECK-ENCODING: [0x08,0x18,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
@@ -737,6 +1027,151 @@ fmls za.d[w9, 7], {z12.d - z15.d}, z11.d // 11000001-01111011-00111001-10001
// CHECK-UNKNOWN: c17b398f <unknown>
+fmls za.d[w8, 0, vgx4], {z0.d - z3.d}, z0.d[0] // 11000001-11010000-10000000-00010000
+// CHECK-INST: fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]
+// CHECK-ENCODING: [0x10,0x80,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08010 <unknown>
+
+fmls za.d[w8, 0], {z0.d - z3.d}, z0.d[0] // 11000001-11010000-10000000-00010000
+// CHECK-INST: fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]
+// CHECK-ENCODING: [0x10,0x80,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08010 <unknown>
+
+fmls za.d[w10, 5, vgx4], {z8.d - z11.d}, z5.d[1] // 11000001-11010101-11000101-00010101
+// CHECK-INST: fmls za.d[w10, 5, vgx4], { z8.d - z11.d }, z5.d[1]
+// CHECK-ENCODING: [0x15,0xc5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5c515 <unknown>
+
+fmls za.d[w10, 5], {z8.d - z11.d}, z5.d[1] // 11000001-11010101-11000101-00010101
+// CHECK-INST: fmls za.d[w10, 5, vgx4], { z8.d - z11.d }, z5.d[1]
+// CHECK-ENCODING: [0x15,0xc5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5c515 <unknown>
+
+fmls za.d[w11, 7, vgx4], {z12.d - z15.d}, z8.d[1] // 11000001-11011000-11100101-10010111
+// CHECK-INST: fmls za.d[w11, 7, vgx4], { z12.d - z15.d }, z8.d[1]
+// CHECK-ENCODING: [0x97,0xe5,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8e597 <unknown>
+
+fmls za.d[w11, 7], {z12.d - z15.d}, z8.d[1] // 11000001-11011000-11100101-10010111
+// CHECK-INST: fmls za.d[w11, 7, vgx4], { z12.d - z15.d }, z8.d[1]
+// CHECK-ENCODING: [0x97,0xe5,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8e597 <unknown>
+
+fmls za.d[w11, 7, vgx4], {z28.d - z31.d}, z15.d[1] // 11000001-11011111-11100111-10010111
+// CHECK-INST: fmls za.d[w11, 7, vgx4], { z28.d - z31.d }, z15.d[1]
+// CHECK-ENCODING: [0x97,0xe7,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfe797 <unknown>
+
+fmls za.d[w11, 7], {z28.d - z31.d}, z15.d[1] // 11000001-11011111-11100111-10010111
+// CHECK-INST: fmls za.d[w11, 7, vgx4], { z28.d - z31.d }, z15.d[1]
+// CHECK-ENCODING: [0x97,0xe7,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfe797 <unknown>
+
+fmls za.d[w8, 5, vgx4], {z16.d - z19.d}, z0.d[1] // 11000001-11010000-10000110-00010101
+// CHECK-INST: fmls za.d[w8, 5, vgx4], { z16.d - z19.d }, z0.d[1]
+// CHECK-ENCODING: [0x15,0x86,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08615 <unknown>
+
+fmls za.d[w8, 5], {z16.d - z19.d}, z0.d[1] // 11000001-11010000-10000110-00010101
+// CHECK-INST: fmls za.d[w8, 5, vgx4], { z16.d - z19.d }, z0.d[1]
+// CHECK-ENCODING: [0x15,0x86,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08615 <unknown>
+
+fmls za.d[w8, 1, vgx4], {z0.d - z3.d}, z14.d[1] // 11000001-11011110-10000100-00010001
+// CHECK-INST: fmls za.d[w8, 1, vgx4], { z0.d - z3.d }, z14.d[1]
+// CHECK-ENCODING: [0x11,0x84,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8411 <unknown>
+
+fmls za.d[w8, 1], {z0.d - z3.d}, z14.d[1] // 11000001-11011110-10000100-00010001
+// CHECK-INST: fmls za.d[w8, 1, vgx4], { z0.d - z3.d }, z14.d[1]
+// CHECK-ENCODING: [0x11,0x84,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8411 <unknown>
+
+fmls za.d[w10, 0, vgx4], {z16.d - z19.d}, z4.d[1] // 11000001-11010100-11000110-00010000
+// CHECK-INST: fmls za.d[w10, 0, vgx4], { z16.d - z19.d }, z4.d[1]
+// CHECK-ENCODING: [0x10,0xc6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4c610 <unknown>
+
+fmls za.d[w10, 0], {z16.d - z19.d}, z4.d[1] // 11000001-11010100-11000110-00010000
+// CHECK-INST: fmls za.d[w10, 0, vgx4], { z16.d - z19.d }, z4.d[1]
+// CHECK-ENCODING: [0x10,0xc6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4c610 <unknown>
+
+fmls za.d[w8, 0, vgx4], {z12.d - z15.d}, z2.d[0] // 11000001-11010010-10000001-10010000
+// CHECK-INST: fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d[0]
+// CHECK-ENCODING: [0x90,0x81,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d28190 <unknown>
+
+fmls za.d[w8, 0], {z12.d - z15.d}, z2.d[0] // 11000001-11010010-10000001-10010000
+// CHECK-INST: fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d[0]
+// CHECK-ENCODING: [0x90,0x81,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d28190 <unknown>
+
+fmls za.d[w10, 1, vgx4], {z0.d - z3.d}, z10.d[0] // 11000001-11011010-11000000-00010001
+// CHECK-INST: fmls za.d[w10, 1, vgx4], { z0.d - z3.d }, z10.d[0]
+// CHECK-ENCODING: [0x11,0xc0,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dac011 <unknown>
+
+fmls za.d[w10, 1], {z0.d - z3.d}, z10.d[0] // 11000001-11011010-11000000-00010001
+// CHECK-INST: fmls za.d[w10, 1, vgx4], { z0.d - z3.d }, z10.d[0]
+// CHECK-ENCODING: [0x11,0xc0,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dac011 <unknown>
+
+fmls za.d[w8, 5, vgx4], {z20.d - z23.d}, z14.d[0] // 11000001-11011110-10000010-10010101
+// CHECK-INST: fmls za.d[w8, 5, vgx4], { z20.d - z23.d }, z14.d[0]
+// CHECK-ENCODING: [0x95,0x82,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8295 <unknown>
+
+fmls za.d[w8, 5], {z20.d - z23.d}, z14.d[0] // 11000001-11011110-10000010-10010101
+// CHECK-INST: fmls za.d[w8, 5, vgx4], { z20.d - z23.d }, z14.d[0]
+// CHECK-ENCODING: [0x95,0x82,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8295 <unknown>
+
+fmls za.d[w11, 2, vgx4], {z8.d - z11.d}, z1.d[1] // 11000001-11010001-11100101-00010010
+// CHECK-INST: fmls za.d[w11, 2, vgx4], { z8.d - z11.d }, z1.d[1]
+// CHECK-ENCODING: [0x12,0xe5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1e512 <unknown>
+
+fmls za.d[w11, 2], {z8.d - z11.d}, z1.d[1] // 11000001-11010001-11100101-00010010
+// CHECK-INST: fmls za.d[w11, 2, vgx4], { z8.d - z11.d }, z1.d[1]
+// CHECK-ENCODING: [0x12,0xe5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1e512 <unknown>
+
+fmls za.d[w9, 7, vgx4], {z12.d - z15.d}, z11.d[0] // 11000001-11011011-10100001-10010111
+// CHECK-INST: fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d[0]
+// CHECK-ENCODING: [0x97,0xa1,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dba197 <unknown>
+
+fmls za.d[w9, 7], {z12.d - z15.d}, z11.d[0] // 11000001-11011011-10100001-10010111
+// CHECK-INST: fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d[0]
+// CHECK-ENCODING: [0x97,0xa1,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dba197 <unknown>
+
+
fmls za.d[w8, 0, vgx4], {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100001-00011000-00001000
// CHECK-INST: fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
// CHECK-ENCODING: [0x08,0x18,0xe1,0xc1]
@@ -1027,6 +1462,151 @@ fmls za.s[w9, 7], {z12.s - z15.s}, z11.s // 11000001-00111011-00111001-10001
// CHECK-UNKNOWN: c13b398f <unknown>
+fmls za.s[w8, 0, vgx4], {z0.s - z3.s}, z0.s[0] // 11000001-01010000-10000000-00010000
+// CHECK-INST: fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]
+// CHECK-ENCODING: [0x10,0x80,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508010 <unknown>
+
+fmls za.s[w8, 0], {z0.s - z3.s}, z0.s[0] // 11000001-01010000-10000000-00010000
+// CHECK-INST: fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]
+// CHECK-ENCODING: [0x10,0x80,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508010 <unknown>
+
+fmls za.s[w10, 5, vgx4], {z8.s - z11.s}, z5.s[1] // 11000001-01010101-11000101-00010101
+// CHECK-INST: fmls za.s[w10, 5, vgx4], { z8.s - z11.s }, z5.s[1]
+// CHECK-ENCODING: [0x15,0xc5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155c515 <unknown>
+
+fmls za.s[w10, 5], {z8.s - z11.s}, z5.s[1] // 11000001-01010101-11000101-00010101
+// CHECK-INST: fmls za.s[w10, 5, vgx4], { z8.s - z11.s }, z5.s[1]
+// CHECK-ENCODING: [0x15,0xc5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155c515 <unknown>
+
+fmls za.s[w11, 7, vgx4], {z12.s - z15.s}, z8.s[3] // 11000001-01011000-11101101-10010111
+// CHECK-INST: fmls za.s[w11, 7, vgx4], { z12.s - z15.s }, z8.s[3]
+// CHECK-ENCODING: [0x97,0xed,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158ed97 <unknown>
+
+fmls za.s[w11, 7], {z12.s - z15.s}, z8.s[3] // 11000001-01011000-11101101-10010111
+// CHECK-INST: fmls za.s[w11, 7, vgx4], { z12.s - z15.s }, z8.s[3]
+// CHECK-ENCODING: [0x97,0xed,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158ed97 <unknown>
+
+fmls za.s[w11, 7, vgx4], {z28.s - z31.s}, z15.s[3] // 11000001-01011111-11101111-10010111
+// CHECK-INST: fmls za.s[w11, 7, vgx4], { z28.s - z31.s }, z15.s[3]
+// CHECK-ENCODING: [0x97,0xef,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fef97 <unknown>
+
+fmls za.s[w11, 7], {z28.s - z31.s}, z15.s[3] // 11000001-01011111-11101111-10010111
+// CHECK-INST: fmls za.s[w11, 7, vgx4], { z28.s - z31.s }, z15.s[3]
+// CHECK-ENCODING: [0x97,0xef,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fef97 <unknown>
+
+fmls za.s[w8, 5, vgx4], {z16.s - z19.s}, z0.s[3] // 11000001-01010000-10001110-00010101
+// CHECK-INST: fmls za.s[w8, 5, vgx4], { z16.s - z19.s }, z0.s[3]
+// CHECK-ENCODING: [0x15,0x8e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508e15 <unknown>
+
+fmls za.s[w8, 5], {z16.s - z19.s}, z0.s[3] // 11000001-01010000-10001110-00010101
+// CHECK-INST: fmls za.s[w8, 5, vgx4], { z16.s - z19.s }, z0.s[3]
+// CHECK-ENCODING: [0x15,0x8e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508e15 <unknown>
+
+fmls za.s[w8, 1, vgx4], {z0.s - z3.s}, z14.s[1] // 11000001-01011110-10000100-00010001
+// CHECK-INST: fmls za.s[w8, 1, vgx4], { z0.s - z3.s }, z14.s[1]
+// CHECK-ENCODING: [0x11,0x84,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8411 <unknown>
+
+fmls za.s[w8, 1], {z0.s - z3.s}, z14.s[1] // 11000001-01011110-10000100-00010001
+// CHECK-INST: fmls za.s[w8, 1, vgx4], { z0.s - z3.s }, z14.s[1]
+// CHECK-ENCODING: [0x11,0x84,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8411 <unknown>
+
+fmls za.s[w10, 0, vgx4], {z16.s - z19.s}, z4.s[1] // 11000001-01010100-11000110-00010000
+// CHECK-INST: fmls za.s[w10, 0, vgx4], { z16.s - z19.s }, z4.s[1]
+// CHECK-ENCODING: [0x10,0xc6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154c610 <unknown>
+
+fmls za.s[w10, 0], {z16.s - z19.s}, z4.s[1] // 11000001-01010100-11000110-00010000
+// CHECK-INST: fmls za.s[w10, 0, vgx4], { z16.s - z19.s }, z4.s[1]
+// CHECK-ENCODING: [0x10,0xc6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154c610 <unknown>
+
+fmls za.s[w8, 0, vgx4], {z12.s - z15.s}, z2.s[2] // 11000001-01010010-10001001-10010000
+// CHECK-INST: fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s[2]
+// CHECK-ENCODING: [0x90,0x89,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1528990 <unknown>
+
+fmls za.s[w8, 0], {z12.s - z15.s}, z2.s[2] // 11000001-01010010-10001001-10010000
+// CHECK-INST: fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s[2]
+// CHECK-ENCODING: [0x90,0x89,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1528990 <unknown>
+
+fmls za.s[w10, 1, vgx4], {z0.s - z3.s}, z10.s[2] // 11000001-01011010-11001000-00010001
+// CHECK-INST: fmls za.s[w10, 1, vgx4], { z0.s - z3.s }, z10.s[2]
+// CHECK-ENCODING: [0x11,0xc8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ac811 <unknown>
+
+fmls za.s[w10, 1], {z0.s - z3.s}, z10.s[2] // 11000001-01011010-11001000-00010001
+// CHECK-INST: fmls za.s[w10, 1, vgx4], { z0.s - z3.s }, z10.s[2]
+// CHECK-ENCODING: [0x11,0xc8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ac811 <unknown>
+
+fmls za.s[w8, 5, vgx4], {z20.s - z23.s}, z14.s[2] // 11000001-01011110-10001010-10010101
+// CHECK-INST: fmls za.s[w8, 5, vgx4], { z20.s - z23.s }, z14.s[2]
+// CHECK-ENCODING: [0x95,0x8a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8a95 <unknown>
+
+fmls za.s[w8, 5], {z20.s - z23.s}, z14.s[2] // 11000001-01011110-10001010-10010101
+// CHECK-INST: fmls za.s[w8, 5, vgx4], { z20.s - z23.s }, z14.s[2]
+// CHECK-ENCODING: [0x95,0x8a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8a95 <unknown>
+
+fmls za.s[w11, 2, vgx4], {z8.s - z11.s}, z1.s[1] // 11000001-01010001-11100101-00010010
+// CHECK-INST: fmls za.s[w11, 2, vgx4], { z8.s - z11.s }, z1.s[1]
+// CHECK-ENCODING: [0x12,0xe5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151e512 <unknown>
+
+fmls za.s[w11, 2], {z8.s - z11.s}, z1.s[1] // 11000001-01010001-11100101-00010010
+// CHECK-INST: fmls za.s[w11, 2, vgx4], { z8.s - z11.s }, z1.s[1]
+// CHECK-ENCODING: [0x12,0xe5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151e512 <unknown>
+
+fmls za.s[w9, 7, vgx4], {z12.s - z15.s}, z11.s[2] // 11000001-01011011-10101001-10010111
+// CHECK-INST: fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s[2]
+// CHECK-ENCODING: [0x97,0xa9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ba997 <unknown>
+
+fmls za.s[w9, 7], {z12.s - z15.s}, z11.s[2] // 11000001-01011011-10101001-10010111
+// CHECK-INST: fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s[2]
+// CHECK-ENCODING: [0x97,0xa9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ba997 <unknown>
+
+
fmls za.s[w8, 0, vgx4], {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100001-00011000-00001000
// CHECK-INST: fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
// CHECK-ENCODING: [0x08,0x18,0xa1,0xc1]
diff --git a/llvm/test/MC/AArch64/SME2/fvdot-diagnostics.s b/llvm/test/MC/AArch64/SME2/fvdot-diagnostics.s
new file mode 100644
index 0000000000000..d991207ee1a73
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fvdot-diagnostics.s
@@ -0,0 +1,69 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+fvdot za.s[w7, 0, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: fvdot za.s[w7, 0, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fvdot za.s[w12, 0, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: fvdot za.s[w12, 0, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select offset
+
+fvdot za.s[w8, -1, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: fvdot za.s[w8, -1, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fvdot za.s[w8, 8, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: fvdot za.s[w8, 8, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+fvdot za.s[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fvdot za.s[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fvdot za.s[w8, 0, vgx2], {z1.h-z2.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
+// CHECK-NEXT: fvdot za.s[w8, 0, vgx2], {z1.h-z2.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Matrix Operand
+
+fvdot za.h[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: fvdot za.h[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector grouping
+
+fvdot za.s[w8, 0, vgx4], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fvdot za.s[w8, 0, vgx4], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid lane index
+
+fvdot za.s[w8, 0, vgx2], {z0.h-z1.h}, z0.h[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]
+// CHECK-NEXT: fvdot za.s[w8, 0, vgx2], {z0.h-z1.h}, z0.h[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fvdot za.s[w8, 0, vgx2], {z0.h-z1.h}, z0.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]
+// CHECK-NEXT: fvdot za.s[w8, 0, vgx2], {z0.h-z1.h}, z0.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/fvdot.s b/llvm/test/MC/AArch64/SME2/fvdot.s
new file mode 100644
index 0000000000000..0b5efb6e61bed
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fvdot.s
@@ -0,0 +1,158 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fvdot za.s[w8, 0, vgx2], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00000000-00001000
+// CHECK-INST: fvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x00,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500008 <unknown>
+
+fvdot za.s[w8, 0], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00000000-00001000
+// CHECK-INST: fvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x00,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500008 <unknown>
+
+fvdot za.s[w10, 5, vgx2], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01000101-01001101
+// CHECK-INST: fvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x4d,0x45,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155454d <unknown>
+
+fvdot za.s[w10, 5], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01000101-01001101
+// CHECK-INST: fvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x4d,0x45,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155454d <unknown>
+
+fvdot za.s[w11, 7, vgx2], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01101101-10001111
+// CHECK-INST: fvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0x8f,0x6d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1586d8f <unknown>
+
+fvdot za.s[w11, 7], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01101101-10001111
+// CHECK-INST: fvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0x8f,0x6d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1586d8f <unknown>
+
+fvdot za.s[w11, 7, vgx2], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01101111-11001111
+// CHECK-INST: fvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xcf,0x6f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f6fcf <unknown>
+
+fvdot za.s[w11, 7], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01101111-11001111
+// CHECK-INST: fvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xcf,0x6f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f6fcf <unknown>
+
+fvdot za.s[w8, 5, vgx2], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00001110-00001101
+// CHECK-INST: fvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x0d,0x0e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500e0d <unknown>
+
+fvdot za.s[w8, 5], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00001110-00001101
+// CHECK-INST: fvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x0d,0x0e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500e0d <unknown>
+
+fvdot za.s[w8, 1, vgx2], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00000100-00001001
+// CHECK-INST: fvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x09,0x04,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0409 <unknown>
+
+fvdot za.s[w8, 1], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00000100-00001001
+// CHECK-INST: fvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x09,0x04,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0409 <unknown>
+
+fvdot za.s[w10, 0, vgx2], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01000110-01001000
+// CHECK-INST: fvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x48,0x46,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1544648 <unknown>
+
+fvdot za.s[w10, 0], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01000110-01001000
+// CHECK-INST: fvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x48,0x46,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1544648 <unknown>
+
+fvdot za.s[w8, 0, vgx2], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00001001-10001000
+// CHECK-INST: fvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0x88,0x09,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1520988 <unknown>
+
+fvdot za.s[w8, 0], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00001001-10001000
+// CHECK-INST: fvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0x88,0x09,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1520988 <unknown>
+
+fvdot za.s[w10, 1, vgx2], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01001000-00001001
+// CHECK-INST: fvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x09,0x48,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a4809 <unknown>
+
+fvdot za.s[w10, 1], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01001000-00001001
+// CHECK-INST: fvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x09,0x48,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a4809 <unknown>
+
+fvdot za.s[w8, 5, vgx2], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00001010-11001101
+// CHECK-INST: fvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xcd,0x0a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0acd <unknown>
+
+fvdot za.s[w8, 5], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00001010-11001101
+// CHECK-INST: fvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xcd,0x0a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0acd <unknown>
+
+fvdot za.s[w11, 2, vgx2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01100101-00001010
+// CHECK-INST: fvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x0a,0x65,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151650a <unknown>
+
+fvdot za.s[w11, 2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01100101-00001010
+// CHECK-INST: fvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x0a,0x65,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151650a <unknown>
+
+fvdot za.s[w9, 7, vgx2], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00101001-10001111
+// CHECK-INST: fvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0x8f,0x29,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b298f <unknown>
+
+fvdot za.s[w9, 7], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00101001-10001111
+// CHECK-INST: fvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0x8f,0x29,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b298f <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/sdot-diagnostics.s b/llvm/test/MC/AArch64/SME2/sdot-diagnostics.s
new file mode 100644
index 0000000000000..65cafebfb6e3f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sdot-diagnostics.s
@@ -0,0 +1,53 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid select register
+
+sdot za.s[w7, 0, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: sdot za.s[w7, 0, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot za.s[w12, 0, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: sdot za.s[w12, 0, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid select offset
+
+sdot za.s[w8, -1], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: sdot za.s[w8, -1], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot za.s[w8, 8], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: sdot za.s[w8, 8], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Out of range element index
+
+sdot za.s[w8, 0], {z0.h-z1.h}, z0.h[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: sdot za.s[w8, 0], {z0.h-z1.h}, z0.h[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot za.s[w8, 0], {z0.h-z3.h}, z0.h[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: sdot za.s[w8, 0], {z0.h-z3.h}, z0.h[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// ZPR range constraint
+
+sdot za.s[w8, 5], {z0.h-z1.h}, z16.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: sdot za.s[w8, 5], {z0.h-z1.h}, z16.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot za.s[w8, 5], {z0.h-z3.h}, z16.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: sdot za.s[w8, 5], {z0.h-z3.h}, z16.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/sdot.s b/llvm/test/MC/AArch64/SME2/sdot.s
new file mode 100644
index 0000000000000..5e621f6d9fa4d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sdot.s
@@ -0,0 +1,882 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2,+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+sme-i16i64 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+sdot za.s[w8, 0, vgx2], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00010000-00000000
+// CHECK-INST: sdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x00,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501000 <unknown>
+
+sdot za.s[w8, 0], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00010000-00000000
+// CHECK-INST: sdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x00,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501000 <unknown>
+
+sdot za.s[w10, 5, vgx2], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01010101-01000101
+// CHECK-INST: sdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x45,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1555545 <unknown>
+
+sdot za.s[w10, 5], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01010101-01000101
+// CHECK-INST: sdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x45,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1555545 <unknown>
+
+sdot za.s[w11, 7, vgx2], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01111101-10000111
+// CHECK-INST: sdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0x87,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587d87 <unknown>
+
+sdot za.s[w11, 7], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01111101-10000111
+// CHECK-INST: sdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0x87,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587d87 <unknown>
+
+sdot za.s[w11, 7, vgx2], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01111111-11000111
+// CHECK-INST: sdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xc7,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7fc7 <unknown>
+
+sdot za.s[w11, 7], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01111111-11000111
+// CHECK-INST: sdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xc7,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7fc7 <unknown>
+
+sdot za.s[w8, 5, vgx2], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00011110-00000101
+// CHECK-INST: sdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x05,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e05 <unknown>
+
+sdot za.s[w8, 5], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00011110-00000101
+// CHECK-INST: sdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x05,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e05 <unknown>
+
+sdot za.s[w8, 1, vgx2], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00010100-00000001
+// CHECK-INST: sdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x01,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1401 <unknown>
+
+sdot za.s[w8, 1], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00010100-00000001
+// CHECK-INST: sdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x01,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1401 <unknown>
+
+sdot za.s[w10, 0, vgx2], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01010110-01000000
+// CHECK-INST: sdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x40,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545640 <unknown>
+
+sdot za.s[w10, 0], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01010110-01000000
+// CHECK-INST: sdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x40,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545640 <unknown>
+
+sdot za.s[w8, 0, vgx2], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00011001-10000000
+// CHECK-INST: sdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0x80,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1521980 <unknown>
+
+sdot za.s[w8, 0], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00011001-10000000
+// CHECK-INST: sdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0x80,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1521980 <unknown>
+
+sdot za.s[w10, 1, vgx2], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01011000-00000001
+// CHECK-INST: sdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x01,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5801 <unknown>
+
+sdot za.s[w10, 1], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01011000-00000001
+// CHECK-INST: sdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x01,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5801 <unknown>
+
+sdot za.s[w8, 5, vgx2], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00011010-11000101
+// CHECK-INST: sdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xc5,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1ac5 <unknown>
+
+sdot za.s[w8, 5], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00011010-11000101
+// CHECK-INST: sdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xc5,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1ac5 <unknown>
+
+sdot za.s[w11, 2, vgx2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01110101-00000010
+// CHECK-INST: sdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x02,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1517502 <unknown>
+
+sdot za.s[w11, 2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01110101-00000010
+// CHECK-INST: sdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x02,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1517502 <unknown>
+
+sdot za.s[w9, 7, vgx2], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00111001-10000111
+// CHECK-INST: sdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0x87,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b3987 <unknown>
+
+sdot za.s[w9, 7], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00111001-10000111
+// CHECK-INST: sdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0x87,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b3987 <unknown>
+
+
+sdot za.s[w8, 0, vgx2], {z0.b, z1.b}, z0.b[0] // 11000001-01010000-00010000-00100000
+// CHECK-INST: sdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]
+// CHECK-ENCODING: [0x20,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501020 <unknown>
+
+sdot za.s[w8, 0], {z0.b, z1.b}, z0.b[0] // 11000001-01010000-00010000-00100000
+// CHECK-INST: sdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]
+// CHECK-ENCODING: [0x20,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501020 <unknown>
+
+sdot za.s[w10, 5, vgx2], {z10.b, z11.b}, z5.b[1] // 11000001-01010101-01010101-01100101
+// CHECK-INST: sdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x65,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1555565 <unknown>
+
+sdot za.s[w10, 5], {z10.b, z11.b}, z5.b[1] // 11000001-01010101-01010101-01100101
+// CHECK-INST: sdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x65,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1555565 <unknown>
+
+sdot za.s[w11, 7, vgx2], {z12.b, z13.b}, z8.b[3] // 11000001-01011000-01111101-10100111
+// CHECK-INST: sdot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]
+// CHECK-ENCODING: [0xa7,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587da7 <unknown>
+
+sdot za.s[w11, 7], {z12.b, z13.b}, z8.b[3] // 11000001-01011000-01111101-10100111
+// CHECK-INST: sdot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]
+// CHECK-ENCODING: [0xa7,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587da7 <unknown>
+
+sdot za.s[w11, 7, vgx2], {z30.b, z31.b}, z15.b[3] // 11000001-01011111-01111111-11100111
+// CHECK-INST: sdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xe7,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7fe7 <unknown>
+
+sdot za.s[w11, 7], {z30.b, z31.b}, z15.b[3] // 11000001-01011111-01111111-11100111
+// CHECK-INST: sdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xe7,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7fe7 <unknown>
+
+sdot za.s[w8, 5, vgx2], {z16.b, z17.b}, z0.b[3] // 11000001-01010000-00011110-00100101
+// CHECK-INST: sdot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]
+// CHECK-ENCODING: [0x25,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e25 <unknown>
+
+sdot za.s[w8, 5], {z16.b, z17.b}, z0.b[3] // 11000001-01010000-00011110-00100101
+// CHECK-INST: sdot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]
+// CHECK-ENCODING: [0x25,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e25 <unknown>
+
+sdot za.s[w8, 1, vgx2], {z0.b, z1.b}, z14.b[1] // 11000001-01011110-00010100-00100001
+// CHECK-INST: sdot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]
+// CHECK-ENCODING: [0x21,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1421 <unknown>
+
+sdot za.s[w8, 1], {z0.b, z1.b}, z14.b[1] // 11000001-01011110-00010100-00100001
+// CHECK-INST: sdot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]
+// CHECK-ENCODING: [0x21,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1421 <unknown>
+
+sdot za.s[w10, 0, vgx2], {z18.b, z19.b}, z4.b[1] // 11000001-01010100-01010110-01100000
+// CHECK-INST: sdot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x60,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545660 <unknown>
+
+sdot za.s[w10, 0], {z18.b, z19.b}, z4.b[1] // 11000001-01010100-01010110-01100000
+// CHECK-INST: sdot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x60,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545660 <unknown>
+
+sdot za.s[w8, 0, vgx2], {z12.b, z13.b}, z2.b[2] // 11000001-01010010-00011001-10100000
+// CHECK-INST: sdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]
+// CHECK-ENCODING: [0xa0,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15219a0 <unknown>
+
+sdot za.s[w8, 0], {z12.b, z13.b}, z2.b[2] // 11000001-01010010-00011001-10100000
+// CHECK-INST: sdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]
+// CHECK-ENCODING: [0xa0,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15219a0 <unknown>
+
+sdot za.s[w10, 1, vgx2], {z0.b, z1.b}, z10.b[2] // 11000001-01011010-01011000-00100001
+// CHECK-INST: sdot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]
+// CHECK-ENCODING: [0x21,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5821 <unknown>
+
+sdot za.s[w10, 1], {z0.b, z1.b}, z10.b[2] // 11000001-01011010-01011000-00100001
+// CHECK-INST: sdot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]
+// CHECK-ENCODING: [0x21,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5821 <unknown>
+
+sdot za.s[w8, 5, vgx2], {z22.b, z23.b}, z14.b[2] // 11000001-01011110-00011010-11100101
+// CHECK-INST: sdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xe5,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1ae5 <unknown>
+
+sdot za.s[w8, 5], {z22.b, z23.b}, z14.b[2] // 11000001-01011110-00011010-11100101
+// CHECK-INST: sdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xe5,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1ae5 <unknown>
+
+sdot za.s[w11, 2, vgx2], {z8.b, z9.b}, z1.b[1] // 11000001-01010001-01110101-00100010
+// CHECK-INST: sdot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]
+// CHECK-ENCODING: [0x22,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1517522 <unknown>
+
+sdot za.s[w11, 2], {z8.b, z9.b}, z1.b[1] // 11000001-01010001-01110101-00100010
+// CHECK-INST: sdot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]
+// CHECK-ENCODING: [0x22,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1517522 <unknown>
+
+sdot za.s[w9, 7, vgx2], {z12.b, z13.b}, z11.b[2] // 11000001-01011011-00111001-10100111
+// CHECK-INST: sdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]
+// CHECK-ENCODING: [0xa7,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b39a7 <unknown>
+
+sdot za.s[w9, 7], {z12.b, z13.b}, z11.b[2] // 11000001-01011011-00111001-10100111
+// CHECK-INST: sdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]
+// CHECK-ENCODING: [0xa7,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b39a7 <unknown>
+
+
+sdot za.d[w8, 0, vgx2], {z0.h, z1.h}, z0.h[0] // 11000001-11010000-00000000-00001000
+// CHECK-INST: sdot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x00,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d00008 <unknown>
+
+sdot za.d[w8, 0], {z0.h, z1.h}, z0.h[0] // 11000001-11010000-00000000-00001000
+// CHECK-INST: sdot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x00,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d00008 <unknown>
+
+sdot za.d[w10, 5, vgx2], {z10.h, z11.h}, z5.h[1] // 11000001-11010101-01000101-01001101
+// CHECK-INST: sdot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x4d,0x45,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5454d <unknown>
+
+sdot za.d[w10, 5], {z10.h, z11.h}, z5.h[1] // 11000001-11010101-01000101-01001101
+// CHECK-INST: sdot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x4d,0x45,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5454d <unknown>
+
+sdot za.d[w11, 7, vgx2], {z12.h, z13.h}, z8.h[1] // 11000001-11011000-01100101-10001111
+// CHECK-INST: sdot za.d[w11, 7, vgx2], { z12.h, z13.h }, z8.h[1]
+// CHECK-ENCODING: [0x8f,0x65,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8658f <unknown>
+
+sdot za.d[w11, 7], {z12.h, z13.h}, z8.h[1] // 11000001-11011000-01100101-10001111
+// CHECK-INST: sdot za.d[w11, 7, vgx2], { z12.h, z13.h }, z8.h[1]
+// CHECK-ENCODING: [0x8f,0x65,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8658f <unknown>
+
+sdot za.d[w11, 7, vgx2], {z30.h, z31.h}, z15.h[1] // 11000001-11011111-01100111-11001111
+// CHECK-INST: sdot za.d[w11, 7, vgx2], { z30.h, z31.h }, z15.h[1]
+// CHECK-ENCODING: [0xcf,0x67,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df67cf <unknown>
+
+sdot za.d[w11, 7], {z30.h, z31.h}, z15.h[1] // 11000001-11011111-01100111-11001111
+// CHECK-INST: sdot za.d[w11, 7, vgx2], { z30.h, z31.h }, z15.h[1]
+// CHECK-ENCODING: [0xcf,0x67,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df67cf <unknown>
+
+sdot za.d[w8, 5, vgx2], {z16.h, z17.h}, z0.h[1] // 11000001-11010000-00000110-00001101
+// CHECK-INST: sdot za.d[w8, 5, vgx2], { z16.h, z17.h }, z0.h[1]
+// CHECK-ENCODING: [0x0d,0x06,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d0060d <unknown>
+
+sdot za.d[w8, 5], {z16.h, z17.h}, z0.h[1] // 11000001-11010000-00000110-00001101
+// CHECK-INST: sdot za.d[w8, 5, vgx2], { z16.h, z17.h }, z0.h[1]
+// CHECK-ENCODING: [0x0d,0x06,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d0060d <unknown>
+
+sdot za.d[w8, 1, vgx2], {z0.h, z1.h}, z14.h[1] // 11000001-11011110-00000100-00001001
+// CHECK-INST: sdot za.d[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x09,0x04,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de0409 <unknown>
+
+sdot za.d[w8, 1], {z0.h, z1.h}, z14.h[1] // 11000001-11011110-00000100-00001001
+// CHECK-INST: sdot za.d[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x09,0x04,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de0409 <unknown>
+
+sdot za.d[w10, 0, vgx2], {z18.h, z19.h}, z4.h[1] // 11000001-11010100-01000110-01001000
+// CHECK-INST: sdot za.d[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x48,0x46,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d44648 <unknown>
+
+sdot za.d[w10, 0], {z18.h, z19.h}, z4.h[1] // 11000001-11010100-01000110-01001000
+// CHECK-INST: sdot za.d[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x48,0x46,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d44648 <unknown>
+
+sdot za.d[w8, 0, vgx2], {z12.h, z13.h}, z2.h[0] // 11000001-11010010-00000001-10001000
+// CHECK-INST: sdot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h[0]
+// CHECK-ENCODING: [0x88,0x01,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d20188 <unknown>
+
+sdot za.d[w8, 0], {z12.h, z13.h}, z2.h[0] // 11000001-11010010-00000001-10001000
+// CHECK-INST: sdot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h[0]
+// CHECK-ENCODING: [0x88,0x01,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d20188 <unknown>
+
+sdot za.d[w10, 1, vgx2], {z0.h, z1.h}, z10.h[0] // 11000001-11011010-01000000-00001001
+// CHECK-INST: sdot za.d[w10, 1, vgx2], { z0.h, z1.h }, z10.h[0]
+// CHECK-ENCODING: [0x09,0x40,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da4009 <unknown>
+
+sdot za.d[w10, 1], {z0.h, z1.h}, z10.h[0] // 11000001-11011010-01000000-00001001
+// CHECK-INST: sdot za.d[w10, 1, vgx2], { z0.h, z1.h }, z10.h[0]
+// CHECK-ENCODING: [0x09,0x40,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da4009 <unknown>
+
+sdot za.d[w8, 5, vgx2], {z22.h, z23.h}, z14.h[0] // 11000001-11011110-00000010-11001101
+// CHECK-INST: sdot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h[0]
+// CHECK-ENCODING: [0xcd,0x02,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de02cd <unknown>
+
+sdot za.d[w8, 5], {z22.h, z23.h}, z14.h[0] // 11000001-11011110-00000010-11001101
+// CHECK-INST: sdot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h[0]
+// CHECK-ENCODING: [0xcd,0x02,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de02cd <unknown>
+
+sdot za.d[w11, 2, vgx2], {z8.h, z9.h}, z1.h[1] // 11000001-11010001-01100101-00001010
+// CHECK-INST: sdot za.d[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x0a,0x65,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1650a <unknown>
+
+sdot za.d[w11, 2], {z8.h, z9.h}, z1.h[1] // 11000001-11010001-01100101-00001010
+// CHECK-INST: sdot za.d[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x0a,0x65,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1650a <unknown>
+
+sdot za.d[w9, 7, vgx2], {z12.h, z13.h}, z11.h[0] // 11000001-11011011-00100001-10001111
+// CHECK-INST: sdot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h[0]
+// CHECK-ENCODING: [0x8f,0x21,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db218f <unknown>
+
+sdot za.d[w9, 7], {z12.h, z13.h}, z11.h[0] // 11000001-11011011-00100001-10001111
+// CHECK-INST: sdot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h[0]
+// CHECK-ENCODING: [0x8f,0x21,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db218f <unknown>
+
+
+sdot za.s[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0] // 11000001-01010000-10010000-00000000
+// CHECK-INST: sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x00,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509000 <unknown>
+
+sdot za.s[w8, 0], {z0.h - z3.h}, z0.h[0] // 11000001-01010000-10010000-00000000
+// CHECK-INST: sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x00,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509000 <unknown>
+
+sdot za.s[w10, 5, vgx4], {z8.h - z11.h}, z5.h[1] // 11000001-01010101-11010101-00000101
+// CHECK-INST: sdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x05,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d505 <unknown>
+
+sdot za.s[w10, 5], {z8.h - z11.h}, z5.h[1] // 11000001-01010101-11010101-00000101
+// CHECK-INST: sdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x05,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d505 <unknown>
+
+sdot za.s[w11, 7, vgx4], {z12.h - z15.h}, z8.h[3] // 11000001-01011000-11111101-10000111
+// CHECK-INST: sdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]
+// CHECK-ENCODING: [0x87,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fd87 <unknown>
+
+sdot za.s[w11, 7], {z12.h - z15.h}, z8.h[3] // 11000001-01011000-11111101-10000111
+// CHECK-INST: sdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]
+// CHECK-ENCODING: [0x87,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fd87 <unknown>
+
+sdot za.s[w11, 7, vgx4], {z28.h - z31.h}, z15.h[3] // 11000001-01011111-11111111-10000111
+// CHECK-INST: sdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]
+// CHECK-ENCODING: [0x87,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fff87 <unknown>
+
+sdot za.s[w11, 7], {z28.h - z31.h}, z15.h[3] // 11000001-01011111-11111111-10000111
+// CHECK-INST: sdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]
+// CHECK-ENCODING: [0x87,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fff87 <unknown>
+
+sdot za.s[w8, 5, vgx4], {z16.h - z19.h}, z0.h[3] // 11000001-01010000-10011110-00000101
+// CHECK-INST: sdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]
+// CHECK-ENCODING: [0x05,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e05 <unknown>
+
+sdot za.s[w8, 5], {z16.h - z19.h}, z0.h[3] // 11000001-01010000-10011110-00000101
+// CHECK-INST: sdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]
+// CHECK-ENCODING: [0x05,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e05 <unknown>
+
+sdot za.s[w8, 1, vgx4], {z0.h - z3.h}, z14.h[1] // 11000001-01011110-10010100-00000001
+// CHECK-INST: sdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x01,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9401 <unknown>
+
+sdot za.s[w8, 1], {z0.h - z3.h}, z14.h[1] // 11000001-01011110-10010100-00000001
+// CHECK-INST: sdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x01,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9401 <unknown>
+
+sdot za.s[w10, 0, vgx4], {z16.h - z19.h}, z4.h[1] // 11000001-01010100-11010110-00000000
+// CHECK-INST: sdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x00,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d600 <unknown>
+
+sdot za.s[w10, 0], {z16.h - z19.h}, z4.h[1] // 11000001-01010100-11010110-00000000
+// CHECK-INST: sdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x00,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d600 <unknown>
+
+sdot za.s[w8, 0, vgx4], {z12.h - z15.h}, z2.h[2] // 11000001-01010010-10011001-10000000
+// CHECK-INST: sdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]
+// CHECK-ENCODING: [0x80,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1529980 <unknown>
+
+sdot za.s[w8, 0], {z12.h - z15.h}, z2.h[2] // 11000001-01010010-10011001-10000000
+// CHECK-INST: sdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]
+// CHECK-ENCODING: [0x80,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1529980 <unknown>
+
+sdot za.s[w10, 1, vgx4], {z0.h - z3.h}, z10.h[2] // 11000001-01011010-11011000-00000001
+// CHECK-INST: sdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]
+// CHECK-ENCODING: [0x01,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad801 <unknown>
+
+sdot za.s[w10, 1], {z0.h - z3.h}, z10.h[2] // 11000001-01011010-11011000-00000001
+// CHECK-INST: sdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]
+// CHECK-ENCODING: [0x01,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad801 <unknown>
+
+sdot za.s[w8, 5, vgx4], {z20.h - z23.h}, z14.h[2] // 11000001-01011110-10011010-10000101
+// CHECK-INST: sdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]
+// CHECK-ENCODING: [0x85,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9a85 <unknown>
+
+sdot za.s[w8, 5], {z20.h - z23.h}, z14.h[2] // 11000001-01011110-10011010-10000101
+// CHECK-INST: sdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]
+// CHECK-ENCODING: [0x85,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9a85 <unknown>
+
+sdot za.s[w11, 2, vgx4], {z8.h - z11.h}, z1.h[1] // 11000001-01010001-11110101-00000010
+// CHECK-INST: sdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x02,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f502 <unknown>
+
+sdot za.s[w11, 2], {z8.h - z11.h}, z1.h[1] // 11000001-01010001-11110101-00000010
+// CHECK-INST: sdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x02,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f502 <unknown>
+
+sdot za.s[w9, 7, vgx4], {z12.h - z15.h}, z11.h[2] // 11000001-01011011-10111001-10000111
+// CHECK-INST: sdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]
+// CHECK-ENCODING: [0x87,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb987 <unknown>
+
+sdot za.s[w9, 7], {z12.h - z15.h}, z11.h[2] // 11000001-01011011-10111001-10000111
+// CHECK-INST: sdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]
+// CHECK-ENCODING: [0x87,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb987 <unknown>
+
+
+sdot za.s[w8, 0, vgx4], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10010000-00100000
+// CHECK-INST: sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+// CHECK-ENCODING: [0x20,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509020 <unknown>
+
+sdot za.s[w8, 0], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10010000-00100000
+// CHECK-INST: sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+// CHECK-ENCODING: [0x20,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509020 <unknown>
+
+sdot za.s[w10, 5, vgx4], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11010101-00100101
+// CHECK-INST: sdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x25,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d525 <unknown>
+
+sdot za.s[w10, 5], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11010101-00100101
+// CHECK-INST: sdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x25,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d525 <unknown>
+
+sdot za.s[w11, 7, vgx4], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11111101-10100111
+// CHECK-INST: sdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
+// CHECK-ENCODING: [0xa7,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fda7 <unknown>
+
+sdot za.s[w11, 7], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11111101-10100111
+// CHECK-INST: sdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
+// CHECK-ENCODING: [0xa7,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fda7 <unknown>
+
+sdot za.s[w11, 7, vgx4], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11111111-10100111
+// CHECK-INST: sdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xa7,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fffa7 <unknown>
+
+sdot za.s[w11, 7], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11111111-10100111
+// CHECK-INST: sdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xa7,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fffa7 <unknown>
+
+sdot za.s[w8, 5, vgx4], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10011110-00100101
+// CHECK-INST: sdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
+// CHECK-ENCODING: [0x25,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e25 <unknown>
+
+sdot za.s[w8, 5], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10011110-00100101
+// CHECK-INST: sdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
+// CHECK-ENCODING: [0x25,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e25 <unknown>
+
+sdot za.s[w8, 1, vgx4], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10010100-00100001
+// CHECK-INST: sdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
+// CHECK-ENCODING: [0x21,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9421 <unknown>
+
+sdot za.s[w8, 1], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10010100-00100001
+// CHECK-INST: sdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
+// CHECK-ENCODING: [0x21,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9421 <unknown>
+
+sdot za.s[w10, 0, vgx4], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11010110-00100000
+// CHECK-INST: sdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x20,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d620 <unknown>
+
+sdot za.s[w10, 0], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11010110-00100000
+// CHECK-INST: sdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x20,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d620 <unknown>
+
+sdot za.s[w8, 0, vgx4], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10011001-10100000
+// CHECK-INST: sdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
+// CHECK-ENCODING: [0xa0,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15299a0 <unknown>
+
+sdot za.s[w8, 0], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10011001-10100000
+// CHECK-INST: sdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
+// CHECK-ENCODING: [0xa0,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15299a0 <unknown>
+
+sdot za.s[w10, 1, vgx4], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11011000-00100001
+// CHECK-INST: sdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
+// CHECK-ENCODING: [0x21,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad821 <unknown>
+
+sdot za.s[w10, 1], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11011000-00100001
+// CHECK-INST: sdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
+// CHECK-ENCODING: [0x21,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad821 <unknown>
+
+sdot za.s[w8, 5, vgx4], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10011010-10100101
+// CHECK-INST: sdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xa5,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9aa5 <unknown>
+
+sdot za.s[w8, 5], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10011010-10100101
+// CHECK-INST: sdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xa5,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9aa5 <unknown>
+
+sdot za.s[w11, 2, vgx4], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11110101-00100010
+// CHECK-INST: sdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
+// CHECK-ENCODING: [0x22,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f522 <unknown>
+
+sdot za.s[w11, 2], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11110101-00100010
+// CHECK-INST: sdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
+// CHECK-ENCODING: [0x22,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f522 <unknown>
+
+sdot za.s[w9, 7, vgx4], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10111001-10100111
+// CHECK-INST: sdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
+// CHECK-ENCODING: [0xa7,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb9a7 <unknown>
+
+sdot za.s[w9, 7], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10111001-10100111
+// CHECK-INST: sdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
+// CHECK-ENCODING: [0xa7,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb9a7 <unknown>
+
+
+sdot za.d[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0] // 11000001-11010000-10000000-00001000
+// CHECK-INST: sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x80,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08008 <unknown>
+
+sdot za.d[w8, 0], {z0.h - z3.h}, z0.h[0] // 11000001-11010000-10000000-00001000
+// CHECK-INST: sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x80,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08008 <unknown>
+
+sdot za.d[w10, 5, vgx4], {z8.h - z11.h}, z5.h[1] // 11000001-11010101-11000101-00001101
+// CHECK-INST: sdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x0d,0xc5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5c50d <unknown>
+
+sdot za.d[w10, 5], {z8.h - z11.h}, z5.h[1] // 11000001-11010101-11000101-00001101
+// CHECK-INST: sdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x0d,0xc5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5c50d <unknown>
+
+sdot za.d[w11, 7, vgx4], {z12.h - z15.h}, z8.h[1] // 11000001-11011000-11100101-10001111
+// CHECK-INST: sdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]
+// CHECK-ENCODING: [0x8f,0xe5,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8e58f <unknown>
+
+sdot za.d[w11, 7], {z12.h - z15.h}, z8.h[1] // 11000001-11011000-11100101-10001111
+// CHECK-INST: sdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]
+// CHECK-ENCODING: [0x8f,0xe5,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8e58f <unknown>
+
+sdot za.d[w11, 7, vgx4], {z28.h - z31.h}, z15.h[1] // 11000001-11011111-11100111-10001111
+// CHECK-INST: sdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]
+// CHECK-ENCODING: [0x8f,0xe7,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfe78f <unknown>
+
+sdot za.d[w11, 7], {z28.h - z31.h}, z15.h[1] // 11000001-11011111-11100111-10001111
+// CHECK-INST: sdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]
+// CHECK-ENCODING: [0x8f,0xe7,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfe78f <unknown>
+
+sdot za.d[w8, 5, vgx4], {z16.h - z19.h}, z0.h[1] // 11000001-11010000-10000110-00001101
+// CHECK-INST: sdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]
+// CHECK-ENCODING: [0x0d,0x86,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d0860d <unknown>
+
+sdot za.d[w8, 5], {z16.h - z19.h}, z0.h[1] // 11000001-11010000-10000110-00001101
+// CHECK-INST: sdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]
+// CHECK-ENCODING: [0x0d,0x86,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d0860d <unknown>
+
+sdot za.d[w8, 1, vgx4], {z0.h - z3.h}, z14.h[1] // 11000001-11011110-10000100-00001001
+// CHECK-INST: sdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x09,0x84,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8409 <unknown>
+
+sdot za.d[w8, 1], {z0.h - z3.h}, z14.h[1] // 11000001-11011110-10000100-00001001
+// CHECK-INST: sdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x09,0x84,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8409 <unknown>
+
+sdot za.d[w10, 0, vgx4], {z16.h - z19.h}, z4.h[1] // 11000001-11010100-11000110-00001000
+// CHECK-INST: sdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x08,0xc6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4c608 <unknown>
+
+sdot za.d[w10, 0], {z16.h - z19.h}, z4.h[1] // 11000001-11010100-11000110-00001000
+// CHECK-INST: sdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x08,0xc6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4c608 <unknown>
+
+sdot za.d[w8, 0, vgx4], {z12.h - z15.h}, z2.h[0] // 11000001-11010010-10000001-10001000
+// CHECK-INST: sdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]
+// CHECK-ENCODING: [0x88,0x81,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d28188 <unknown>
+
+sdot za.d[w8, 0], {z12.h - z15.h}, z2.h[0] // 11000001-11010010-10000001-10001000
+// CHECK-INST: sdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]
+// CHECK-ENCODING: [0x88,0x81,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d28188 <unknown>
+
+sdot za.d[w10, 1, vgx4], {z0.h - z3.h}, z10.h[0] // 11000001-11011010-11000000-00001001
+// CHECK-INST: sdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]
+// CHECK-ENCODING: [0x09,0xc0,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dac009 <unknown>
+
+sdot za.d[w10, 1], {z0.h - z3.h}, z10.h[0] // 11000001-11011010-11000000-00001001
+// CHECK-INST: sdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]
+// CHECK-ENCODING: [0x09,0xc0,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dac009 <unknown>
+
+sdot za.d[w8, 5, vgx4], {z20.h - z23.h}, z14.h[0] // 11000001-11011110-10000010-10001101
+// CHECK-INST: sdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]
+// CHECK-ENCODING: [0x8d,0x82,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de828d <unknown>
+
+sdot za.d[w8, 5], {z20.h - z23.h}, z14.h[0] // 11000001-11011110-10000010-10001101
+// CHECK-INST: sdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]
+// CHECK-ENCODING: [0x8d,0x82,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de828d <unknown>
+
+sdot za.d[w11, 2, vgx4], {z8.h - z11.h}, z1.h[1] // 11000001-11010001-11100101-00001010
+// CHECK-INST: sdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x0a,0xe5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1e50a <unknown>
+
+sdot za.d[w11, 2], {z8.h - z11.h}, z1.h[1] // 11000001-11010001-11100101-00001010
+// CHECK-INST: sdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x0a,0xe5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1e50a <unknown>
+
+sdot za.d[w9, 7, vgx4], {z12.h - z15.h}, z11.h[0] // 11000001-11011011-10100001-10001111
+// CHECK-INST: sdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]
+// CHECK-ENCODING: [0x8f,0xa1,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dba18f <unknown>
+
+sdot za.d[w9, 7], {z12.h - z15.h}, z11.h[0] // 11000001-11011011-10100001-10001111
+// CHECK-INST: sdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]
+// CHECK-ENCODING: [0x8f,0xa1,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dba18f <unknown>
diff --git a/llvm/test/MC/AArch64/SME2/sudot-diagnostics.s b/llvm/test/MC/AArch64/SME2/sudot-diagnostics.s
new file mode 100644
index 0000000000000..eb8ea51177f6c
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sudot-diagnostics.s
@@ -0,0 +1,53 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid select register
+
+sudot za.s[w7, 0, vgx4], {z0.b-z3.b}, z0.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: sudot za.s[w7, 0, vgx4], {z0.b-z3.b}, z0.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sudot za.s[w12, 0, vgx2], {z0.b-z1.b}, z0.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: sudot za.s[w12, 0, vgx2], {z0.b-z1.b}, z0.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid select offset
+
+sudot za.s[w8, 8], {z0.b-z1.b}, z0.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: sudot za.s[w8, 8], {z0.b-z1.b}, z0.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sudot za.s[w8, -1], {z0.b-z3.b}, z0.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: sudot za.s[w8, -1], {z0.b-z3.b}, z0.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Out of range element index
+
+sudot za.s[w8, 0], {z0.b-z1.b}, z0.b[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: sudot za.s[w8, 0], {z0.b-z1.b}, z0.b[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sudot za.s[w8, 0], {z0.b-z3.b}, z0.b[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: sudot za.s[w8, 0], {z0.b-z3.b}, z0.b[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// ZPR range constraint
+
+sudot za.s[w8, 5], {z0.b-z1.b}, z16.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: sudot za.s[w8, 5], {z0.b-z1.b}, z16.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sudot za.s[w8, 5], {z0.b-z3.b}, z16.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: sudot za.s[w8, 5], {z0.b-z3.b}, z16.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/sudot.s b/llvm/test/MC/AArch64/SME2/sudot.s
new file mode 100644
index 0000000000000..6aa16eee1afbf
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sudot.s
@@ -0,0 +1,303 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+sudot za.s[w8, 0, vgx2], {z0.b, z1.b}, z0.b[0] // 11000001-01010000-00010000-00111000
+// CHECK-INST: sudot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]
+// CHECK-ENCODING: [0x38,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501038 <unknown>
+
+sudot za.s[w8, 0], {z0.b, z1.b}, z0.b[0] // 11000001-01010000-00010000-00111000
+// CHECK-INST: sudot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]
+// CHECK-ENCODING: [0x38,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501038 <unknown>
+
+sudot za.s[w10, 5, vgx2], {z10.b, z11.b}, z5.b[1] // 11000001-01010101-01010101-01111101
+// CHECK-INST: sudot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x7d,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155557d <unknown>
+
+sudot za.s[w10, 5], {z10.b, z11.b}, z5.b[1] // 11000001-01010101-01010101-01111101
+// CHECK-INST: sudot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x7d,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155557d <unknown>
+
+sudot za.s[w11, 7, vgx2], {z12.b, z13.b}, z8.b[3] // 11000001-01011000-01111101-10111111
+// CHECK-INST: sudot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]
+// CHECK-ENCODING: [0xbf,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587dbf <unknown>
+
+sudot za.s[w11, 7], {z12.b, z13.b}, z8.b[3] // 11000001-01011000-01111101-10111111
+// CHECK-INST: sudot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]
+// CHECK-ENCODING: [0xbf,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587dbf <unknown>
+
+sudot za.s[w11, 7, vgx2], {z30.b, z31.b}, z15.b[3] // 11000001-01011111-01111111-11111111
+// CHECK-INST: sudot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xff,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7fff <unknown>
+
+sudot za.s[w11, 7], {z30.b, z31.b}, z15.b[3] // 11000001-01011111-01111111-11111111
+// CHECK-INST: sudot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xff,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7fff <unknown>
+
+sudot za.s[w8, 5, vgx2], {z16.b, z17.b}, z0.b[3] // 11000001-01010000-00011110-00111101
+// CHECK-INST: sudot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]
+// CHECK-ENCODING: [0x3d,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e3d <unknown>
+
+sudot za.s[w8, 5], {z16.b, z17.b}, z0.b[3] // 11000001-01010000-00011110-00111101
+// CHECK-INST: sudot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]
+// CHECK-ENCODING: [0x3d,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e3d <unknown>
+
+sudot za.s[w8, 1, vgx2], {z0.b, z1.b}, z14.b[1] // 11000001-01011110-00010100-00111001
+// CHECK-INST: sudot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]
+// CHECK-ENCODING: [0x39,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1439 <unknown>
+
+sudot za.s[w8, 1], {z0.b, z1.b}, z14.b[1] // 11000001-01011110-00010100-00111001
+// CHECK-INST: sudot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]
+// CHECK-ENCODING: [0x39,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1439 <unknown>
+
+sudot za.s[w10, 0, vgx2], {z18.b, z19.b}, z4.b[1] // 11000001-01010100-01010110-01111000
+// CHECK-INST: sudot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x78,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545678 <unknown>
+
+sudot za.s[w10, 0], {z18.b, z19.b}, z4.b[1] // 11000001-01010100-01010110-01111000
+// CHECK-INST: sudot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x78,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545678 <unknown>
+
+sudot za.s[w8, 0, vgx2], {z12.b, z13.b}, z2.b[2] // 11000001-01010010-00011001-10111000
+// CHECK-INST: sudot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]
+// CHECK-ENCODING: [0xb8,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15219b8 <unknown>
+
+sudot za.s[w8, 0], {z12.b, z13.b}, z2.b[2] // 11000001-01010010-00011001-10111000
+// CHECK-INST: sudot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]
+// CHECK-ENCODING: [0xb8,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15219b8 <unknown>
+
+sudot za.s[w10, 1, vgx2], {z0.b, z1.b}, z10.b[2] // 11000001-01011010-01011000-00111001
+// CHECK-INST: sudot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]
+// CHECK-ENCODING: [0x39,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5839 <unknown>
+
+sudot za.s[w10, 1], {z0.b, z1.b}, z10.b[2] // 11000001-01011010-01011000-00111001
+// CHECK-INST: sudot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]
+// CHECK-ENCODING: [0x39,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5839 <unknown>
+
+sudot za.s[w8, 5, vgx2], {z22.b, z23.b}, z14.b[2] // 11000001-01011110-00011010-11111101
+// CHECK-INST: sudot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xfd,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1afd <unknown>
+
+sudot za.s[w8, 5], {z22.b, z23.b}, z14.b[2] // 11000001-01011110-00011010-11111101
+// CHECK-INST: sudot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xfd,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1afd <unknown>
+
+sudot za.s[w11, 2, vgx2], {z8.b, z9.b}, z1.b[1] // 11000001-01010001-01110101-00111010
+// CHECK-INST: sudot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]
+// CHECK-ENCODING: [0x3a,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151753a <unknown>
+
+sudot za.s[w11, 2], {z8.b, z9.b}, z1.b[1] // 11000001-01010001-01110101-00111010
+// CHECK-INST: sudot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]
+// CHECK-ENCODING: [0x3a,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151753a <unknown>
+
+sudot za.s[w9, 7, vgx2], {z12.b, z13.b}, z11.b[2] // 11000001-01011011-00111001-10111111
+// CHECK-INST: sudot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]
+// CHECK-ENCODING: [0xbf,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b39bf <unknown>
+
+sudot za.s[w9, 7], {z12.b, z13.b}, z11.b[2] // 11000001-01011011-00111001-10111111
+// CHECK-INST: sudot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]
+// CHECK-ENCODING: [0xbf,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b39bf <unknown>
+
+
+sudot za.s[w8, 0, vgx4], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10010000-00111000
+// CHECK-INST: sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+// CHECK-ENCODING: [0x38,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509038 <unknown>
+
+sudot za.s[w8, 0], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10010000-00111000
+// CHECK-INST: sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+// CHECK-ENCODING: [0x38,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509038 <unknown>
+
+sudot za.s[w10, 5, vgx4], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11010101-00111101
+// CHECK-INST: sudot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x3d,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d53d <unknown>
+
+sudot za.s[w10, 5], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11010101-00111101
+// CHECK-INST: sudot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x3d,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d53d <unknown>
+
+sudot za.s[w11, 7, vgx4], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11111101-10111111
+// CHECK-INST: sudot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
+// CHECK-ENCODING: [0xbf,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fdbf <unknown>
+
+sudot za.s[w11, 7], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11111101-10111111
+// CHECK-INST: sudot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
+// CHECK-ENCODING: [0xbf,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fdbf <unknown>
+
+sudot za.s[w11, 7, vgx4], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11111111-10111111
+// CHECK-INST: sudot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xbf,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fffbf <unknown>
+
+sudot za.s[w11, 7], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11111111-10111111
+// CHECK-INST: sudot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xbf,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fffbf <unknown>
+
+sudot za.s[w8, 5, vgx4], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10011110-00111101
+// CHECK-INST: sudot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
+// CHECK-ENCODING: [0x3d,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e3d <unknown>
+
+sudot za.s[w8, 5], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10011110-00111101
+// CHECK-INST: sudot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
+// CHECK-ENCODING: [0x3d,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e3d <unknown>
+
+sudot za.s[w8, 1, vgx4], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10010100-00111001
+// CHECK-INST: sudot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
+// CHECK-ENCODING: [0x39,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9439 <unknown>
+
+sudot za.s[w8, 1], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10010100-00111001
+// CHECK-INST: sudot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
+// CHECK-ENCODING: [0x39,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9439 <unknown>
+
+sudot za.s[w10, 0, vgx4], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11010110-00111000
+// CHECK-INST: sudot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x38,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d638 <unknown>
+
+sudot za.s[w10, 0], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11010110-00111000
+// CHECK-INST: sudot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x38,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d638 <unknown>
+
+sudot za.s[w8, 0, vgx4], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10011001-10111000
+// CHECK-INST: sudot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
+// CHECK-ENCODING: [0xb8,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15299b8 <unknown>
+
+sudot za.s[w8, 0], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10011001-10111000
+// CHECK-INST: sudot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
+// CHECK-ENCODING: [0xb8,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15299b8 <unknown>
+
+sudot za.s[w10, 1, vgx4], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11011000-00111001
+// CHECK-INST: sudot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
+// CHECK-ENCODING: [0x39,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad839 <unknown>
+
+sudot za.s[w10, 1], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11011000-00111001
+// CHECK-INST: sudot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
+// CHECK-ENCODING: [0x39,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad839 <unknown>
+
+sudot za.s[w8, 5, vgx4], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10011010-10111101
+// CHECK-INST: sudot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xbd,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9abd <unknown>
+
+sudot za.s[w8, 5], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10011010-10111101
+// CHECK-INST: sudot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xbd,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9abd <unknown>
+
+sudot za.s[w11, 2, vgx4], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11110101-00111010
+// CHECK-INST: sudot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
+// CHECK-ENCODING: [0x3a,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f53a <unknown>
+
+sudot za.s[w11, 2], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11110101-00111010
+// CHECK-INST: sudot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
+// CHECK-ENCODING: [0x3a,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f53a <unknown>
+
+sudot za.s[w9, 7, vgx4], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10111001-10111111
+// CHECK-INST: sudot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
+// CHECK-ENCODING: [0xbf,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb9bf <unknown>
+
+sudot za.s[w9, 7], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10111001-10111111
+// CHECK-INST: sudot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
+// CHECK-ENCODING: [0xbf,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb9bf <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/suvdot-diagnostics.s b/llvm/test/MC/AArch64/SME2/suvdot-diagnostics.s
new file mode 100644
index 0000000000000..a58d45f141491
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/suvdot-diagnostics.s
@@ -0,0 +1,69 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Out of range index offset
+
+suvdot za.s[w8, 8, vgx4], {z0.b-z3.b}, z0.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: suvdot za.s[w8, 8, vgx4], {z0.b-z3.b}, z0.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+suvdot za.s[w8, -1, vgx4], {z0.b-z3.b}, z0.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: suvdot za.s[w8, -1, vgx4], {z0.b-z3.b}, z0.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+suvdot za.s[w7, 0, vgx4], {z4.b-z7.b}, z0.b[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: suvdot za.s[w7, 0, vgx4], {z4.b-z7.b}, z0.b[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+suvdot za.s[w12, 0, vgx4], {z8.b-z11.b}, z5.b[5]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: suvdot za.s[w12, 0, vgx4], {z8.b-z11.b}, z5.b[5]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+suvdot za.s[w8, 0, vgx4], {z0.b-z4.b}, z0.b[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: suvdot za.s[w8, 0, vgx4], {z0.b-z4.b}, z0.b[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+suvdot za.s[w8, 0, vgx4], {z1.b-z4.b}, z15.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element type
+// CHECK-NEXT: suvdot za.s[w8, 0, vgx4], {z1.b-z4.b}, z15.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Matrix Operand
+
+suvdot za.h[w8, 0, vgx4], {z0.b-z3.b}, z4.b[7]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: suvdot za.h[w8, 0, vgx4], {z0.b-z3.b}, z4.b[7]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector grouping
+
+suvdot za.s[w8, 0, vgx2], {z0.b-z3.b}, z14.b[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: suvdot za.s[w8, 0, vgx2], {z0.b-z3.b}, z14.b[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid lane index
+
+suvdot za.s[w8, 0, vgx4], {z0.b-z3.b}, z14.b[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]
+// CHECK-NEXT: suvdot za.s[w8, 0, vgx4], {z0.b-z3.b}, z14.b[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+suvdot za.s[w8, 0, vgx4], {z0.b-z3.b}, z14.b[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]
+// CHECK-NEXT: suvdot za.s[w8, 0, vgx4], {z0.b-z3.b}, z14.b[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/suvdot.s b/llvm/test/MC/AArch64/SME2/suvdot.s
new file mode 100644
index 0000000000000..42a33ceea7eb3
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/suvdot.s
@@ -0,0 +1,158 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+suvdot za.s[w8, 0, vgx4], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10000000-00111000
+// CHECK-INST: suvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+// CHECK-ENCODING: [0x38,0x80,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508038 <unknown>
+
+suvdot za.s[w8, 0], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10000000-00111000
+// CHECK-INST: suvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+// CHECK-ENCODING: [0x38,0x80,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508038 <unknown>
+
+suvdot za.s[w10, 5, vgx4], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11000101-00111101
+// CHECK-INST: suvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x3d,0xc5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155c53d <unknown>
+
+suvdot za.s[w10, 5], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11000101-00111101
+// CHECK-INST: suvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x3d,0xc5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155c53d <unknown>
+
+suvdot za.s[w11, 7, vgx4], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11101101-10111111
+// CHECK-INST: suvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
+// CHECK-ENCODING: [0xbf,0xed,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158edbf <unknown>
+
+suvdot za.s[w11, 7], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11101101-10111111
+// CHECK-INST: suvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
+// CHECK-ENCODING: [0xbf,0xed,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158edbf <unknown>
+
+suvdot za.s[w11, 7, vgx4], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11101111-10111111
+// CHECK-INST: suvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xbf,0xef,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fefbf <unknown>
+
+suvdot za.s[w11, 7], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11101111-10111111
+// CHECK-INST: suvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xbf,0xef,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fefbf <unknown>
+
+suvdot za.s[w8, 5, vgx4], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10001110-00111101
+// CHECK-INST: suvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
+// CHECK-ENCODING: [0x3d,0x8e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508e3d <unknown>
+
+suvdot za.s[w8, 5], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10001110-00111101
+// CHECK-INST: suvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
+// CHECK-ENCODING: [0x3d,0x8e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508e3d <unknown>
+
+suvdot za.s[w8, 1, vgx4], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10000100-00111001
+// CHECK-INST: suvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
+// CHECK-ENCODING: [0x39,0x84,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8439 <unknown>
+
+suvdot za.s[w8, 1], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10000100-00111001
+// CHECK-INST: suvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
+// CHECK-ENCODING: [0x39,0x84,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8439 <unknown>
+
+suvdot za.s[w10, 0, vgx4], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11000110-00111000
+// CHECK-INST: suvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x38,0xc6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154c638 <unknown>
+
+suvdot za.s[w10, 0], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11000110-00111000
+// CHECK-INST: suvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x38,0xc6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154c638 <unknown>
+
+suvdot za.s[w8, 0, vgx4], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10001001-10111000
+// CHECK-INST: suvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
+// CHECK-ENCODING: [0xb8,0x89,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15289b8 <unknown>
+
+suvdot za.s[w8, 0], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10001001-10111000
+// CHECK-INST: suvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
+// CHECK-ENCODING: [0xb8,0x89,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15289b8 <unknown>
+
+suvdot za.s[w10, 1, vgx4], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11001000-00111001
+// CHECK-INST: suvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
+// CHECK-ENCODING: [0x39,0xc8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ac839 <unknown>
+
+suvdot za.s[w10, 1], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11001000-00111001
+// CHECK-INST: suvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
+// CHECK-ENCODING: [0x39,0xc8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ac839 <unknown>
+
+suvdot za.s[w8, 5, vgx4], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10001010-10111101
+// CHECK-INST: suvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xbd,0x8a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8abd <unknown>
+
+suvdot za.s[w8, 5], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10001010-10111101
+// CHECK-INST: suvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xbd,0x8a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8abd <unknown>
+
+suvdot za.s[w11, 2, vgx4], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11100101-00111010
+// CHECK-INST: suvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
+// CHECK-ENCODING: [0x3a,0xe5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151e53a <unknown>
+
+suvdot za.s[w11, 2], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11100101-00111010
+// CHECK-INST: suvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
+// CHECK-ENCODING: [0x3a,0xe5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151e53a <unknown>
+
+suvdot za.s[w9, 7, vgx4], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10101001-10111111
+// CHECK-INST: suvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
+// CHECK-ENCODING: [0xbf,0xa9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ba9bf <unknown>
+
+suvdot za.s[w9, 7], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10101001-10111111
+// CHECK-INST: suvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
+// CHECK-ENCODING: [0xbf,0xa9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ba9bf <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/svdot-diagnostics.s b/llvm/test/MC/AArch64/SME2/svdot-diagnostics.s
new file mode 100644
index 0000000000000..614b3f6552f15
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/svdot-diagnostics.s
@@ -0,0 +1,51 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Out of range index offset
+
+svdot za.s[w8, 8, vgx4], {z0.b-z3.b}, z0.b[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: svdot za.s[w8, 8, vgx4], {z0.b-z3.b}, z0.b[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+svdot za.s[w8, -1, vgx4], {z0.b-z3.b}, z0.b[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: svdot za.s[w8, -1, vgx4], {z0.b-z3.b}, z0.b[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+svdot za.s[w7, 7, vgx2], {z0.h-z1.h}, z0.h[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: svdot za.s[w7, 7, vgx2], {z0.h-z1.h}, z0.h[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+svdot za.d[w8, 0, vgx4], {z0.h-z4.h}, z0.h[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: svdot za.d[w8, 0, vgx4], {z0.h-z4.h}, z0.h[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+svdot za.s[w8, 0, vgx4], {z1.b-z4.b}, z0.b[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: svdot za.s[w8, 0, vgx4], {z1.b-z4.b}, z0.b[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Matrix Operand
+
+svdot za.b[w8, 0, vgx4], {z0.h-z3.h}, z4.h[7]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: svdot za.b[w8, 0, vgx4], {z0.h-z3.h}, z4.h[7]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector grouping
+
+svdot za.s[w8, 0, vgx2], {z0.b-z3.b}, z14.b[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: svdot za.s[w8, 0, vgx2], {z0.b-z3.b}, z14.b[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/svdot.s b/llvm/test/MC/AArch64/SME2/svdot.s
new file mode 100644
index 0000000000000..cd1e05f3e326f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/svdot.s
@@ -0,0 +1,448 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2,+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+sme-i16i64 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+svdot za.s[w8, 0, vgx2], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00000000-00100000
+// CHECK-INST: svdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x20,0x00,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500020 <unknown>
+
+svdot za.s[w8, 0], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00000000-00100000
+// CHECK-INST: svdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x20,0x00,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500020 <unknown>
+
+svdot za.s[w10, 5, vgx2], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01000101-01100101
+// CHECK-INST: svdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x65,0x45,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1554565 <unknown>
+
+svdot za.s[w10, 5], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01000101-01100101
+// CHECK-INST: svdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x65,0x45,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1554565 <unknown>
+
+svdot za.s[w11, 7, vgx2], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01101101-10100111
+// CHECK-INST: svdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0xa7,0x6d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1586da7 <unknown>
+
+svdot za.s[w11, 7], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01101101-10100111
+// CHECK-INST: svdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0xa7,0x6d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1586da7 <unknown>
+
+svdot za.s[w11, 7, vgx2], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01101111-11100111
+// CHECK-INST: svdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xe7,0x6f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f6fe7 <unknown>
+
+svdot za.s[w11, 7], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01101111-11100111
+// CHECK-INST: svdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xe7,0x6f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f6fe7 <unknown>
+
+svdot za.s[w8, 5, vgx2], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00001110-00100101
+// CHECK-INST: svdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x25,0x0e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500e25 <unknown>
+
+svdot za.s[w8, 5], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00001110-00100101
+// CHECK-INST: svdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x25,0x0e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500e25 <unknown>
+
+svdot za.s[w8, 1, vgx2], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00000100-00100001
+// CHECK-INST: svdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x21,0x04,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0421 <unknown>
+
+svdot za.s[w8, 1], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00000100-00100001
+// CHECK-INST: svdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x21,0x04,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0421 <unknown>
+
+svdot za.s[w10, 0, vgx2], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01000110-01100000
+// CHECK-INST: svdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x60,0x46,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1544660 <unknown>
+
+svdot za.s[w10, 0], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01000110-01100000
+// CHECK-INST: svdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x60,0x46,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1544660 <unknown>
+
+svdot za.s[w8, 0, vgx2], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00001001-10100000
+// CHECK-INST: svdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0xa0,0x09,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15209a0 <unknown>
+
+svdot za.s[w8, 0], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00001001-10100000
+// CHECK-INST: svdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0xa0,0x09,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15209a0 <unknown>
+
+svdot za.s[w10, 1, vgx2], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01001000-00100001
+// CHECK-INST: svdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x21,0x48,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a4821 <unknown>
+
+svdot za.s[w10, 1], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01001000-00100001
+// CHECK-INST: svdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x21,0x48,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a4821 <unknown>
+
+svdot za.s[w8, 5, vgx2], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00001010-11100101
+// CHECK-INST: svdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xe5,0x0a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0ae5 <unknown>
+
+svdot za.s[w8, 5], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00001010-11100101
+// CHECK-INST: svdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xe5,0x0a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0ae5 <unknown>
+
+svdot za.s[w11, 2, vgx2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01100101-00100010
+// CHECK-INST: svdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x22,0x65,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1516522 <unknown>
+
+svdot za.s[w11, 2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01100101-00100010
+// CHECK-INST: svdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x22,0x65,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1516522 <unknown>
+
+svdot za.s[w9, 7, vgx2], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00101001-10100111
+// CHECK-INST: svdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0xa7,0x29,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b29a7 <unknown>
+
+svdot za.s[w9, 7], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00101001-10100111
+// CHECK-INST: svdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0xa7,0x29,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b29a7 <unknown>
+
+
+svdot za.s[w8, 0, vgx4], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10000000-00100000
+// CHECK-INST: svdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+// CHECK-ENCODING: [0x20,0x80,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508020 <unknown>
+
+svdot za.s[w8, 0], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10000000-00100000
+// CHECK-INST: svdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+// CHECK-ENCODING: [0x20,0x80,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508020 <unknown>
+
+svdot za.s[w10, 5, vgx4], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11000101-00100101
+// CHECK-INST: svdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x25,0xc5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155c525 <unknown>
+
+svdot za.s[w10, 5], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11000101-00100101
+// CHECK-INST: svdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x25,0xc5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155c525 <unknown>
+
+svdot za.s[w11, 7, vgx4], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11101101-10100111
+// CHECK-INST: svdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
+// CHECK-ENCODING: [0xa7,0xed,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158eda7 <unknown>
+
+svdot za.s[w11, 7], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11101101-10100111
+// CHECK-INST: svdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
+// CHECK-ENCODING: [0xa7,0xed,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158eda7 <unknown>
+
+svdot za.s[w11, 7, vgx4], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11101111-10100111
+// CHECK-INST: svdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xa7,0xef,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fefa7 <unknown>
+
+svdot za.s[w11, 7], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11101111-10100111
+// CHECK-INST: svdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xa7,0xef,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fefa7 <unknown>
+
+svdot za.s[w8, 5, vgx4], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10001110-00100101
+// CHECK-INST: svdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
+// CHECK-ENCODING: [0x25,0x8e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508e25 <unknown>
+
+svdot za.s[w8, 5], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10001110-00100101
+// CHECK-INST: svdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
+// CHECK-ENCODING: [0x25,0x8e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508e25 <unknown>
+
+svdot za.s[w8, 1, vgx4], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10000100-00100001
+// CHECK-INST: svdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
+// CHECK-ENCODING: [0x21,0x84,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8421 <unknown>
+
+svdot za.s[w8, 1], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10000100-00100001
+// CHECK-INST: svdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
+// CHECK-ENCODING: [0x21,0x84,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8421 <unknown>
+
+svdot za.s[w10, 0, vgx4], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11000110-00100000
+// CHECK-INST: svdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x20,0xc6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154c620 <unknown>
+
+svdot za.s[w10, 0], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11000110-00100000
+// CHECK-INST: svdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x20,0xc6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154c620 <unknown>
+
+svdot za.s[w8, 0, vgx4], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10001001-10100000
+// CHECK-INST: svdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
+// CHECK-ENCODING: [0xa0,0x89,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15289a0 <unknown>
+
+svdot za.s[w8, 0], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10001001-10100000
+// CHECK-INST: svdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
+// CHECK-ENCODING: [0xa0,0x89,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15289a0 <unknown>
+
+svdot za.s[w10, 1, vgx4], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11001000-00100001
+// CHECK-INST: svdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
+// CHECK-ENCODING: [0x21,0xc8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ac821 <unknown>
+
+svdot za.s[w10, 1], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11001000-00100001
+// CHECK-INST: svdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
+// CHECK-ENCODING: [0x21,0xc8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ac821 <unknown>
+
+svdot za.s[w8, 5, vgx4], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10001010-10100101
+// CHECK-INST: svdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xa5,0x8a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8aa5 <unknown>
+
+svdot za.s[w8, 5], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10001010-10100101
+// CHECK-INST: svdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xa5,0x8a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8aa5 <unknown>
+
+svdot za.s[w11, 2, vgx4], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11100101-00100010
+// CHECK-INST: svdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
+// CHECK-ENCODING: [0x22,0xe5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151e522 <unknown>
+
+svdot za.s[w11, 2], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11100101-00100010
+// CHECK-INST: svdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
+// CHECK-ENCODING: [0x22,0xe5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151e522 <unknown>
+
+svdot za.s[w9, 7, vgx4], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10101001-10100111
+// CHECK-INST: svdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
+// CHECK-ENCODING: [0xa7,0xa9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ba9a7 <unknown>
+
+svdot za.s[w9, 7], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10101001-10100111
+// CHECK-INST: svdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
+// CHECK-ENCODING: [0xa7,0xa9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ba9a7 <unknown>
+
+
+svdot za.d[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0] // 11000001-11010000-10001000-00001000
+// CHECK-INST: svdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x88,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08808 <unknown>
+
+svdot za.d[w8, 0], {z0.h - z3.h}, z0.h[0] // 11000001-11010000-10001000-00001000
+// CHECK-INST: svdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x08,0x88,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08808 <unknown>
+
+svdot za.d[w10, 5, vgx4], {z8.h - z11.h}, z5.h[1] // 11000001-11010101-11001101-00001101
+// CHECK-INST: svdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x0d,0xcd,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5cd0d <unknown>
+
+svdot za.d[w10, 5], {z8.h - z11.h}, z5.h[1] // 11000001-11010101-11001101-00001101
+// CHECK-INST: svdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x0d,0xcd,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5cd0d <unknown>
+
+svdot za.d[w11, 7, vgx4], {z12.h - z15.h}, z8.h[1] // 11000001-11011000-11101101-10001111
+// CHECK-INST: svdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]
+// CHECK-ENCODING: [0x8f,0xed,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8ed8f <unknown>
+
+svdot za.d[w11, 7], {z12.h - z15.h}, z8.h[1] // 11000001-11011000-11101101-10001111
+// CHECK-INST: svdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]
+// CHECK-ENCODING: [0x8f,0xed,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8ed8f <unknown>
+
+svdot za.d[w11, 7, vgx4], {z28.h - z31.h}, z15.h[1] // 11000001-11011111-11101111-10001111
+// CHECK-INST: svdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]
+// CHECK-ENCODING: [0x8f,0xef,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfef8f <unknown>
+
+svdot za.d[w11, 7], {z28.h - z31.h}, z15.h[1] // 11000001-11011111-11101111-10001111
+// CHECK-INST: svdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]
+// CHECK-ENCODING: [0x8f,0xef,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfef8f <unknown>
+
+svdot za.d[w8, 5, vgx4], {z16.h - z19.h}, z0.h[1] // 11000001-11010000-10001110-00001101
+// CHECK-INST: svdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]
+// CHECK-ENCODING: [0x0d,0x8e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08e0d <unknown>
+
+svdot za.d[w8, 5], {z16.h - z19.h}, z0.h[1] // 11000001-11010000-10001110-00001101
+// CHECK-INST: svdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]
+// CHECK-ENCODING: [0x0d,0x8e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08e0d <unknown>
+
+svdot za.d[w8, 1, vgx4], {z0.h - z3.h}, z14.h[1] // 11000001-11011110-10001100-00001001
+// CHECK-INST: svdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x09,0x8c,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8c09 <unknown>
+
+svdot za.d[w8, 1], {z0.h - z3.h}, z14.h[1] // 11000001-11011110-10001100-00001001
+// CHECK-INST: svdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x09,0x8c,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8c09 <unknown>
+
+svdot za.d[w10, 0, vgx4], {z16.h - z19.h}, z4.h[1] // 11000001-11010100-11001110-00001000
+// CHECK-INST: svdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x08,0xce,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4ce08 <unknown>
+
+svdot za.d[w10, 0], {z16.h - z19.h}, z4.h[1] // 11000001-11010100-11001110-00001000
+// CHECK-INST: svdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x08,0xce,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4ce08 <unknown>
+
+svdot za.d[w8, 0, vgx4], {z12.h - z15.h}, z2.h[0] // 11000001-11010010-10001001-10001000
+// CHECK-INST: svdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]
+// CHECK-ENCODING: [0x88,0x89,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d28988 <unknown>
+
+svdot za.d[w8, 0], {z12.h - z15.h}, z2.h[0] // 11000001-11010010-10001001-10001000
+// CHECK-INST: svdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]
+// CHECK-ENCODING: [0x88,0x89,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d28988 <unknown>
+
+svdot za.d[w10, 1, vgx4], {z0.h - z3.h}, z10.h[0] // 11000001-11011010-11001000-00001001
+// CHECK-INST: svdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]
+// CHECK-ENCODING: [0x09,0xc8,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dac809 <unknown>
+
+svdot za.d[w10, 1], {z0.h - z3.h}, z10.h[0] // 11000001-11011010-11001000-00001001
+// CHECK-INST: svdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]
+// CHECK-ENCODING: [0x09,0xc8,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dac809 <unknown>
+
+svdot za.d[w8, 5, vgx4], {z20.h - z23.h}, z14.h[0] // 11000001-11011110-10001010-10001101
+// CHECK-INST: svdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]
+// CHECK-ENCODING: [0x8d,0x8a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8a8d <unknown>
+
+svdot za.d[w8, 5], {z20.h - z23.h}, z14.h[0] // 11000001-11011110-10001010-10001101
+// CHECK-INST: svdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]
+// CHECK-ENCODING: [0x8d,0x8a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8a8d <unknown>
+
+svdot za.d[w11, 2, vgx4], {z8.h - z11.h}, z1.h[1] // 11000001-11010001-11101101-00001010
+// CHECK-INST: svdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x0a,0xed,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1ed0a <unknown>
+
+svdot za.d[w11, 2], {z8.h - z11.h}, z1.h[1] // 11000001-11010001-11101101-00001010
+// CHECK-INST: svdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x0a,0xed,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1ed0a <unknown>
+
+svdot za.d[w9, 7, vgx4], {z12.h - z15.h}, z11.h[0] // 11000001-11011011-10101001-10001111
+// CHECK-INST: svdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]
+// CHECK-ENCODING: [0x8f,0xa9,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dba98f <unknown>
+
+svdot za.d[w9, 7], {z12.h - z15.h}, z11.h[0] // 11000001-11011011-10101001-10001111
+// CHECK-INST: svdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]
+// CHECK-ENCODING: [0x8f,0xa9,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dba98f <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/udot-diagnostics.s b/llvm/test/MC/AArch64/SME2/udot-diagnostics.s
new file mode 100644
index 0000000000000..01ae9ec363c6b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/udot-diagnostics.s
@@ -0,0 +1,53 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid select register
+
+udot za.s[w7, 0, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: udot za.s[w7, 0, vgx4], {z0.h-z3.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot za.s[w12, 0, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: udot za.s[w12, 0, vgx2], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid select offset
+
+udot za.s[w8, 8], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: udot za.s[w8, 8], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot za.s[w8, -1], {z0.h-z1.h}, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: udot za.s[w8, -1], {z0.h-z1.h}, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Out of range element index
+
+udot za.s[w8, 0], {z0.h-z1.h}, z0.h[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: udot za.s[w8, 0], {z0.h-z1.h}, z0.h[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot za.s[w8, 0], {z0.h-z3.h}, z0.h[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: udot za.s[w8, 0], {z0.h-z3.h}, z0.h[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// ZPR range constraint
+
+udot za.s[w8, 5], {z0.h-z1.h}, z16.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: udot za.s[w8, 5], {z0.h-z1.h}, z16.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot za.s[w8, 5], {z0.h-z3.h}, z16.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+// CHECK-NEXT: udot za.s[w8, 5], {z0.h-z3.h}, z16.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/udot.s b/llvm/test/MC/AArch64/SME2/udot.s
new file mode 100644
index 0000000000000..3132a4c1813aa
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/udot.s
@@ -0,0 +1,883 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2,+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+sme-i16i64 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+udot za.s[w8, 0, vgx2], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00010000-00010000
+// CHECK-INST: udot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x10,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501010 <unknown>
+
+udot za.s[w8, 0], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00010000-00010000
+// CHECK-INST: udot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x10,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501010 <unknown>
+
+udot za.s[w10, 5, vgx2], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01010101-01010101
+// CHECK-INST: udot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x55,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1555555 <unknown>
+
+udot za.s[w10, 5], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01010101-01010101
+// CHECK-INST: udot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x55,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1555555 <unknown>
+
+udot za.s[w11, 7, vgx2], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01111101-10010111
+// CHECK-INST: udot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0x97,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587d97 <unknown>
+
+udot za.s[w11, 7], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01111101-10010111
+// CHECK-INST: udot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0x97,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587d97 <unknown>
+
+udot za.s[w11, 7, vgx2], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01111111-11010111
+// CHECK-INST: udot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xd7,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7fd7 <unknown>
+
+udot za.s[w11, 7], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01111111-11010111
+// CHECK-INST: udot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xd7,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7fd7 <unknown>
+
+udot za.s[w8, 5, vgx2], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00011110-00010101
+// CHECK-INST: udot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x15,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e15 <unknown>
+
+udot za.s[w8, 5], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00011110-00010101
+// CHECK-INST: udot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x15,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e15 <unknown>
+
+udot za.s[w8, 1, vgx2], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00010100-00010001
+// CHECK-INST: udot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x11,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1411 <unknown>
+
+udot za.s[w8, 1], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00010100-00010001
+// CHECK-INST: udot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x11,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1411 <unknown>
+
+udot za.s[w10, 0, vgx2], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01010110-01010000
+// CHECK-INST: udot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x50,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545650 <unknown>
+
+udot za.s[w10, 0], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01010110-01010000
+// CHECK-INST: udot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x50,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545650 <unknown>
+
+udot za.s[w8, 0, vgx2], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00011001-10010000
+// CHECK-INST: udot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0x90,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1521990 <unknown>
+
+udot za.s[w8, 0], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00011001-10010000
+// CHECK-INST: udot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0x90,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1521990 <unknown>
+
+udot za.s[w10, 1, vgx2], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01011000-00010001
+// CHECK-INST: udot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x11,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5811 <unknown>
+
+udot za.s[w10, 1], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01011000-00010001
+// CHECK-INST: udot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x11,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5811 <unknown>
+
+udot za.s[w8, 5, vgx2], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00011010-11010101
+// CHECK-INST: udot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xd5,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1ad5 <unknown>
+
+udot za.s[w8, 5], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00011010-11010101
+// CHECK-INST: udot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xd5,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1ad5 <unknown>
+
+udot za.s[w11, 2, vgx2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01110101-00010010
+// CHECK-INST: udot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x12,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1517512 <unknown>
+
+udot za.s[w11, 2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01110101-00010010
+// CHECK-INST: udot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x12,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1517512 <unknown>
+
+udot za.s[w9, 7, vgx2], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00111001-10010111
+// CHECK-INST: udot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0x97,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b3997 <unknown>
+
+udot za.s[w9, 7], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00111001-10010111
+// CHECK-INST: udot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0x97,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b3997 <unknown>
+
+
+udot za.s[w8, 0, vgx2], {z0.b, z1.b}, z0.b[0] // 11000001-01010000-00010000-00110000
+// CHECK-INST: udot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]
+// CHECK-ENCODING: [0x30,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501030 <unknown>
+
+udot za.s[w8, 0], {z0.b, z1.b}, z0.b[0] // 11000001-01010000-00010000-00110000
+// CHECK-INST: udot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]
+// CHECK-ENCODING: [0x30,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501030 <unknown>
+
+udot za.s[w10, 5, vgx2], {z10.b, z11.b}, z5.b[1] // 11000001-01010101-01010101-01110101
+// CHECK-INST: udot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x75,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1555575 <unknown>
+
+udot za.s[w10, 5], {z10.b, z11.b}, z5.b[1] // 11000001-01010101-01010101-01110101
+// CHECK-INST: udot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x75,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1555575 <unknown>
+
+udot za.s[w11, 7, vgx2], {z12.b, z13.b}, z8.b[3] // 11000001-01011000-01111101-10110111
+// CHECK-INST: udot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]
+// CHECK-ENCODING: [0xb7,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587db7 <unknown>
+
+udot za.s[w11, 7], {z12.b, z13.b}, z8.b[3] // 11000001-01011000-01111101-10110111
+// CHECK-INST: udot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]
+// CHECK-ENCODING: [0xb7,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587db7 <unknown>
+
+udot za.s[w11, 7, vgx2], {z30.b, z31.b}, z15.b[3] // 11000001-01011111-01111111-11110111
+// CHECK-INST: udot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xf7,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7ff7 <unknown>
+
+udot za.s[w11, 7], {z30.b, z31.b}, z15.b[3] // 11000001-01011111-01111111-11110111
+// CHECK-INST: udot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xf7,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7ff7 <unknown>
+
+udot za.s[w8, 5, vgx2], {z16.b, z17.b}, z0.b[3] // 11000001-01010000-00011110-00110101
+// CHECK-INST: udot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]
+// CHECK-ENCODING: [0x35,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e35 <unknown>
+
+udot za.s[w8, 5], {z16.b, z17.b}, z0.b[3] // 11000001-01010000-00011110-00110101
+// CHECK-INST: udot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]
+// CHECK-ENCODING: [0x35,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e35 <unknown>
+
+udot za.s[w8, 1, vgx2], {z0.b, z1.b}, z14.b[1] // 11000001-01011110-00010100-00110001
+// CHECK-INST: udot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]
+// CHECK-ENCODING: [0x31,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1431 <unknown>
+
+udot za.s[w8, 1], {z0.b, z1.b}, z14.b[1] // 11000001-01011110-00010100-00110001
+// CHECK-INST: udot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]
+// CHECK-ENCODING: [0x31,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1431 <unknown>
+
+udot za.s[w10, 0, vgx2], {z18.b, z19.b}, z4.b[1] // 11000001-01010100-01010110-01110000
+// CHECK-INST: udot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x70,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545670 <unknown>
+
+udot za.s[w10, 0], {z18.b, z19.b}, z4.b[1] // 11000001-01010100-01010110-01110000
+// CHECK-INST: udot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x70,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545670 <unknown>
+
+udot za.s[w8, 0, vgx2], {z12.b, z13.b}, z2.b[2] // 11000001-01010010-00011001-10110000
+// CHECK-INST: udot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]
+// CHECK-ENCODING: [0xb0,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15219b0 <unknown>
+
+udot za.s[w8, 0], {z12.b, z13.b}, z2.b[2] // 11000001-01010010-00011001-10110000
+// CHECK-INST: udot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]
+// CHECK-ENCODING: [0xb0,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15219b0 <unknown>
+
+udot za.s[w10, 1, vgx2], {z0.b, z1.b}, z10.b[2] // 11000001-01011010-01011000-00110001
+// CHECK-INST: udot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]
+// CHECK-ENCODING: [0x31,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5831 <unknown>
+
+udot za.s[w10, 1], {z0.b, z1.b}, z10.b[2] // 11000001-01011010-01011000-00110001
+// CHECK-INST: udot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]
+// CHECK-ENCODING: [0x31,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5831 <unknown>
+
+udot za.s[w8, 5, vgx2], {z22.b, z23.b}, z14.b[2] // 11000001-01011110-00011010-11110101
+// CHECK-INST: udot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xf5,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1af5 <unknown>
+
+udot za.s[w8, 5], {z22.b, z23.b}, z14.b[2] // 11000001-01011110-00011010-11110101
+// CHECK-INST: udot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xf5,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1af5 <unknown>
+
+udot za.s[w11, 2, vgx2], {z8.b, z9.b}, z1.b[1] // 11000001-01010001-01110101-00110010
+// CHECK-INST: udot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]
+// CHECK-ENCODING: [0x32,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1517532 <unknown>
+
+udot za.s[w11, 2], {z8.b, z9.b}, z1.b[1] // 11000001-01010001-01110101-00110010
+// CHECK-INST: udot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]
+// CHECK-ENCODING: [0x32,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1517532 <unknown>
+
+udot za.s[w9, 7, vgx2], {z12.b, z13.b}, z11.b[2] // 11000001-01011011-00111001-10110111
+// CHECK-INST: udot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]
+// CHECK-ENCODING: [0xb7,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b39b7 <unknown>
+
+udot za.s[w9, 7], {z12.b, z13.b}, z11.b[2] // 11000001-01011011-00111001-10110111
+// CHECK-INST: udot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]
+// CHECK-ENCODING: [0xb7,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b39b7 <unknown>
+
+
+udot za.d[w8, 0, vgx2], {z0.h, z1.h}, z0.h[0] // 11000001-11010000-00000000-00011000
+// CHECK-INST: udot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x00,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d00018 <unknown>
+
+udot za.d[w8, 0], {z0.h, z1.h}, z0.h[0] // 11000001-11010000-00000000-00011000
+// CHECK-INST: udot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x00,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d00018 <unknown>
+
+udot za.d[w10, 5, vgx2], {z10.h, z11.h}, z5.h[1] // 11000001-11010101-01000101-01011101
+// CHECK-INST: udot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x5d,0x45,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5455d <unknown>
+
+udot za.d[w10, 5], {z10.h, z11.h}, z5.h[1] // 11000001-11010101-01000101-01011101
+// CHECK-INST: udot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x5d,0x45,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5455d <unknown>
+
+udot za.d[w11, 7, vgx2], {z12.h, z13.h}, z8.h[1] // 11000001-11011000-01100101-10011111
+// CHECK-INST: udot za.d[w11, 7, vgx2], { z12.h, z13.h }, z8.h[1]
+// CHECK-ENCODING: [0x9f,0x65,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8659f <unknown>
+
+udot za.d[w11, 7], {z12.h, z13.h}, z8.h[1] // 11000001-11011000-01100101-10011111
+// CHECK-INST: udot za.d[w11, 7, vgx2], { z12.h, z13.h }, z8.h[1]
+// CHECK-ENCODING: [0x9f,0x65,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8659f <unknown>
+
+udot za.d[w11, 7, vgx2], {z30.h, z31.h}, z15.h[1] // 11000001-11011111-01100111-11011111
+// CHECK-INST: udot za.d[w11, 7, vgx2], { z30.h, z31.h }, z15.h[1]
+// CHECK-ENCODING: [0xdf,0x67,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df67df <unknown>
+
+udot za.d[w11, 7], {z30.h, z31.h}, z15.h[1] // 11000001-11011111-01100111-11011111
+// CHECK-INST: udot za.d[w11, 7, vgx2], { z30.h, z31.h }, z15.h[1]
+// CHECK-ENCODING: [0xdf,0x67,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1df67df <unknown>
+
+udot za.d[w8, 5, vgx2], {z16.h, z17.h}, z0.h[1] // 11000001-11010000-00000110-00011101
+// CHECK-INST: udot za.d[w8, 5, vgx2], { z16.h, z17.h }, z0.h[1]
+// CHECK-ENCODING: [0x1d,0x06,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d0061d <unknown>
+
+udot za.d[w8, 5], {z16.h, z17.h}, z0.h[1] // 11000001-11010000-00000110-00011101
+// CHECK-INST: udot za.d[w8, 5, vgx2], { z16.h, z17.h }, z0.h[1]
+// CHECK-ENCODING: [0x1d,0x06,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d0061d <unknown>
+
+udot za.d[w8, 1, vgx2], {z0.h, z1.h}, z14.h[1] // 11000001-11011110-00000100-00011001
+// CHECK-INST: udot za.d[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x19,0x04,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de0419 <unknown>
+
+udot za.d[w8, 1], {z0.h, z1.h}, z14.h[1] // 11000001-11011110-00000100-00011001
+// CHECK-INST: udot za.d[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x19,0x04,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de0419 <unknown>
+
+udot za.d[w10, 0, vgx2], {z18.h, z19.h}, z4.h[1] // 11000001-11010100-01000110-01011000
+// CHECK-INST: udot za.d[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x58,0x46,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d44658 <unknown>
+
+udot za.d[w10, 0], {z18.h, z19.h}, z4.h[1] // 11000001-11010100-01000110-01011000
+// CHECK-INST: udot za.d[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x58,0x46,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d44658 <unknown>
+
+udot za.d[w8, 0, vgx2], {z12.h, z13.h}, z2.h[0] // 11000001-11010010-00000001-10011000
+// CHECK-INST: udot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h[0]
+// CHECK-ENCODING: [0x98,0x01,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d20198 <unknown>
+
+udot za.d[w8, 0], {z12.h, z13.h}, z2.h[0] // 11000001-11010010-00000001-10011000
+// CHECK-INST: udot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h[0]
+// CHECK-ENCODING: [0x98,0x01,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d20198 <unknown>
+
+udot za.d[w10, 1, vgx2], {z0.h, z1.h}, z10.h[0] // 11000001-11011010-01000000-00011001
+// CHECK-INST: udot za.d[w10, 1, vgx2], { z0.h, z1.h }, z10.h[0]
+// CHECK-ENCODING: [0x19,0x40,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da4019 <unknown>
+
+udot za.d[w10, 1], {z0.h, z1.h}, z10.h[0] // 11000001-11011010-01000000-00011001
+// CHECK-INST: udot za.d[w10, 1, vgx2], { z0.h, z1.h }, z10.h[0]
+// CHECK-ENCODING: [0x19,0x40,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1da4019 <unknown>
+
+udot za.d[w8, 5, vgx2], {z22.h, z23.h}, z14.h[0] // 11000001-11011110-00000010-11011101
+// CHECK-INST: udot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h[0]
+// CHECK-ENCODING: [0xdd,0x02,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de02dd <unknown>
+
+udot za.d[w8, 5], {z22.h, z23.h}, z14.h[0] // 11000001-11011110-00000010-11011101
+// CHECK-INST: udot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h[0]
+// CHECK-ENCODING: [0xdd,0x02,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de02dd <unknown>
+
+udot za.d[w11, 2, vgx2], {z8.h, z9.h}, z1.h[1] // 11000001-11010001-01100101-00011010
+// CHECK-INST: udot za.d[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x1a,0x65,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1651a <unknown>
+
+udot za.d[w11, 2], {z8.h, z9.h}, z1.h[1] // 11000001-11010001-01100101-00011010
+// CHECK-INST: udot za.d[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x1a,0x65,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1651a <unknown>
+
+udot za.d[w9, 7, vgx2], {z12.h, z13.h}, z11.h[0] // 11000001-11011011-00100001-10011111
+// CHECK-INST: udot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h[0]
+// CHECK-ENCODING: [0x9f,0x21,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db219f <unknown>
+
+udot za.d[w9, 7], {z12.h, z13.h}, z11.h[0] // 11000001-11011011-00100001-10011111
+// CHECK-INST: udot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h[0]
+// CHECK-ENCODING: [0x9f,0x21,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1db219f <unknown>
+
+
+udot za.s[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0] // 11000001-01010000-10010000-00010000
+// CHECK-INST: udot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x10,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509010 <unknown>
+
+udot za.s[w8, 0], {z0.h - z3.h}, z0.h[0] // 11000001-01010000-10010000-00010000
+// CHECK-INST: udot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x10,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509010 <unknown>
+
+udot za.s[w10, 5, vgx4], {z8.h - z11.h}, z5.h[1] // 11000001-01010101-11010101-00010101
+// CHECK-INST: udot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x15,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d515 <unknown>
+
+udot za.s[w10, 5], {z8.h - z11.h}, z5.h[1] // 11000001-01010101-11010101-00010101
+// CHECK-INST: udot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x15,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d515 <unknown>
+
+udot za.s[w11, 7, vgx4], {z12.h - z15.h}, z8.h[3] // 11000001-01011000-11111101-10010111
+// CHECK-INST: udot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]
+// CHECK-ENCODING: [0x97,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fd97 <unknown>
+
+udot za.s[w11, 7], {z12.h - z15.h}, z8.h[3] // 11000001-01011000-11111101-10010111
+// CHECK-INST: udot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]
+// CHECK-ENCODING: [0x97,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fd97 <unknown>
+
+udot za.s[w11, 7, vgx4], {z28.h - z31.h}, z15.h[3] // 11000001-01011111-11111111-10010111
+// CHECK-INST: udot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]
+// CHECK-ENCODING: [0x97,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fff97 <unknown>
+
+udot za.s[w11, 7], {z28.h - z31.h}, z15.h[3] // 11000001-01011111-11111111-10010111
+// CHECK-INST: udot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]
+// CHECK-ENCODING: [0x97,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fff97 <unknown>
+
+udot za.s[w8, 5, vgx4], {z16.h - z19.h}, z0.h[3] // 11000001-01010000-10011110-00010101
+// CHECK-INST: udot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]
+// CHECK-ENCODING: [0x15,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e15 <unknown>
+
+udot za.s[w8, 5], {z16.h - z19.h}, z0.h[3] // 11000001-01010000-10011110-00010101
+// CHECK-INST: udot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]
+// CHECK-ENCODING: [0x15,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e15 <unknown>
+
+udot za.s[w8, 1, vgx4], {z0.h - z3.h}, z14.h[1] // 11000001-01011110-10010100-00010001
+// CHECK-INST: udot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x11,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9411 <unknown>
+
+udot za.s[w8, 1], {z0.h - z3.h}, z14.h[1] // 11000001-01011110-10010100-00010001
+// CHECK-INST: udot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x11,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9411 <unknown>
+
+udot za.s[w10, 0, vgx4], {z16.h - z19.h}, z4.h[1] // 11000001-01010100-11010110-00010000
+// CHECK-INST: udot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x10,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d610 <unknown>
+
+udot za.s[w10, 0], {z16.h - z19.h}, z4.h[1] // 11000001-01010100-11010110-00010000
+// CHECK-INST: udot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x10,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d610 <unknown>
+
+udot za.s[w8, 0, vgx4], {z12.h - z15.h}, z2.h[2] // 11000001-01010010-10011001-10010000
+// CHECK-INST: udot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]
+// CHECK-ENCODING: [0x90,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1529990 <unknown>
+
+udot za.s[w8, 0], {z12.h - z15.h}, z2.h[2] // 11000001-01010010-10011001-10010000
+// CHECK-INST: udot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]
+// CHECK-ENCODING: [0x90,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1529990 <unknown>
+
+udot za.s[w10, 1, vgx4], {z0.h - z3.h}, z10.h[2] // 11000001-01011010-11011000-00010001
+// CHECK-INST: udot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]
+// CHECK-ENCODING: [0x11,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad811 <unknown>
+
+udot za.s[w10, 1], {z0.h - z3.h}, z10.h[2] // 11000001-01011010-11011000-00010001
+// CHECK-INST: udot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]
+// CHECK-ENCODING: [0x11,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad811 <unknown>
+
+udot za.s[w8, 5, vgx4], {z20.h - z23.h}, z14.h[2] // 11000001-01011110-10011010-10010101
+// CHECK-INST: udot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]
+// CHECK-ENCODING: [0x95,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9a95 <unknown>
+
+udot za.s[w8, 5], {z20.h - z23.h}, z14.h[2] // 11000001-01011110-10011010-10010101
+// CHECK-INST: udot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]
+// CHECK-ENCODING: [0x95,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9a95 <unknown>
+
+udot za.s[w11, 2, vgx4], {z8.h - z11.h}, z1.h[1] // 11000001-01010001-11110101-00010010
+// CHECK-INST: udot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x12,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f512 <unknown>
+
+udot za.s[w11, 2], {z8.h - z11.h}, z1.h[1] // 11000001-01010001-11110101-00010010
+// CHECK-INST: udot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x12,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f512 <unknown>
+
+udot za.s[w9, 7, vgx4], {z12.h - z15.h}, z11.h[2] // 11000001-01011011-10111001-10010111
+// CHECK-INST: udot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]
+// CHECK-ENCODING: [0x97,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb997 <unknown>
+
+udot za.s[w9, 7], {z12.h - z15.h}, z11.h[2] // 11000001-01011011-10111001-10010111
+// CHECK-INST: udot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]
+// CHECK-ENCODING: [0x97,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb997 <unknown>
+
+
+udot za.s[w8, 0, vgx4], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10010000-00110000
+// CHECK-INST: udot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+// CHECK-ENCODING: [0x30,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509030 <unknown>
+
+udot za.s[w8, 0], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10010000-00110000
+// CHECK-INST: udot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+// CHECK-ENCODING: [0x30,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509030 <unknown>
+
+udot za.s[w10, 5, vgx4], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11010101-00110101
+// CHECK-INST: udot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x35,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d535 <unknown>
+
+udot za.s[w10, 5], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11010101-00110101
+// CHECK-INST: udot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x35,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d535 <unknown>
+
+udot za.s[w11, 7, vgx4], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11111101-10110111
+// CHECK-INST: udot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
+// CHECK-ENCODING: [0xb7,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fdb7 <unknown>
+
+udot za.s[w11, 7], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11111101-10110111
+// CHECK-INST: udot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
+// CHECK-ENCODING: [0xb7,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fdb7 <unknown>
+
+udot za.s[w11, 7, vgx4], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11111111-10110111
+// CHECK-INST: udot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xb7,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fffb7 <unknown>
+
+udot za.s[w11, 7], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11111111-10110111
+// CHECK-INST: udot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xb7,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fffb7 <unknown>
+
+udot za.s[w8, 5, vgx4], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10011110-00110101
+// CHECK-INST: udot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
+// CHECK-ENCODING: [0x35,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e35 <unknown>
+
+udot za.s[w8, 5], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10011110-00110101
+// CHECK-INST: udot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
+// CHECK-ENCODING: [0x35,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e35 <unknown>
+
+udot za.s[w8, 1, vgx4], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10010100-00110001
+// CHECK-INST: udot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
+// CHECK-ENCODING: [0x31,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9431 <unknown>
+
+udot za.s[w8, 1], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10010100-00110001
+// CHECK-INST: udot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
+// CHECK-ENCODING: [0x31,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9431 <unknown>
+
+udot za.s[w10, 0, vgx4], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11010110-00110000
+// CHECK-INST: udot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x30,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d630 <unknown>
+
+udot za.s[w10, 0], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11010110-00110000
+// CHECK-INST: udot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x30,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d630 <unknown>
+
+udot za.s[w8, 0, vgx4], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10011001-10110000
+// CHECK-INST: udot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
+// CHECK-ENCODING: [0xb0,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15299b0 <unknown>
+
+udot za.s[w8, 0], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10011001-10110000
+// CHECK-INST: udot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
+// CHECK-ENCODING: [0xb0,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15299b0 <unknown>
+
+udot za.s[w10, 1, vgx4], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11011000-00110001
+// CHECK-INST: udot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
+// CHECK-ENCODING: [0x31,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad831 <unknown>
+
+udot za.s[w10, 1], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11011000-00110001
+// CHECK-INST: udot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
+// CHECK-ENCODING: [0x31,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad831 <unknown>
+
+udot za.s[w8, 5, vgx4], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10011010-10110101
+// CHECK-INST: udot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xb5,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9ab5 <unknown>
+
+udot za.s[w8, 5], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10011010-10110101
+// CHECK-INST: udot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xb5,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9ab5 <unknown>
+
+udot za.s[w11, 2, vgx4], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11110101-00110010
+// CHECK-INST: udot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
+// CHECK-ENCODING: [0x32,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f532 <unknown>
+
+udot za.s[w11, 2], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11110101-00110010
+// CHECK-INST: udot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
+// CHECK-ENCODING: [0x32,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f532 <unknown>
+
+udot za.s[w9, 7, vgx4], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10111001-10110111
+// CHECK-INST: udot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
+// CHECK-ENCODING: [0xb7,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb9b7 <unknown>
+
+udot za.s[w9, 7], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10111001-10110111
+// CHECK-INST: udot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
+// CHECK-ENCODING: [0xb7,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb9b7 <unknown>
+
+
+udot za.d[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0] // 11000001-11010000-10000000-00011000
+// CHECK-INST: udot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x80,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08018 <unknown>
+
+udot za.d[w8, 0], {z0.h - z3.h}, z0.h[0] // 11000001-11010000-10000000-00011000
+// CHECK-INST: udot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x80,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08018 <unknown>
+
+udot za.d[w10, 5, vgx4], {z8.h - z11.h}, z5.h[1] // 11000001-11010101-11000101-00011101
+// CHECK-INST: udot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x1d,0xc5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5c51d <unknown>
+
+udot za.d[w10, 5], {z8.h - z11.h}, z5.h[1] // 11000001-11010101-11000101-00011101
+// CHECK-INST: udot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x1d,0xc5,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5c51d <unknown>
+
+udot za.d[w11, 7, vgx4], {z12.h - z15.h}, z8.h[1] // 11000001-11011000-11100101-10011111
+// CHECK-INST: udot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]
+// CHECK-ENCODING: [0x9f,0xe5,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8e59f <unknown>
+
+udot za.d[w11, 7], {z12.h - z15.h}, z8.h[1] // 11000001-11011000-11100101-10011111
+// CHECK-INST: udot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]
+// CHECK-ENCODING: [0x9f,0xe5,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8e59f <unknown>
+
+udot za.d[w11, 7, vgx4], {z28.h - z31.h}, z15.h[1] // 11000001-11011111-11100111-10011111
+// CHECK-INST: udot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]
+// CHECK-ENCODING: [0x9f,0xe7,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfe79f <unknown>
+
+udot za.d[w11, 7], {z28.h - z31.h}, z15.h[1] // 11000001-11011111-11100111-10011111
+// CHECK-INST: udot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]
+// CHECK-ENCODING: [0x9f,0xe7,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfe79f <unknown>
+
+udot za.d[w8, 5, vgx4], {z16.h - z19.h}, z0.h[1] // 11000001-11010000-10000110-00011101
+// CHECK-INST: udot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]
+// CHECK-ENCODING: [0x1d,0x86,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d0861d <unknown>
+
+udot za.d[w8, 5], {z16.h - z19.h}, z0.h[1] // 11000001-11010000-10000110-00011101
+// CHECK-INST: udot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]
+// CHECK-ENCODING: [0x1d,0x86,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d0861d <unknown>
+
+udot za.d[w8, 1, vgx4], {z0.h - z3.h}, z14.h[1] // 11000001-11011110-10000100-00011001
+// CHECK-INST: udot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x19,0x84,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8419 <unknown>
+
+udot za.d[w8, 1], {z0.h - z3.h}, z14.h[1] // 11000001-11011110-10000100-00011001
+// CHECK-INST: udot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x19,0x84,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8419 <unknown>
+
+udot za.d[w10, 0, vgx4], {z16.h - z19.h}, z4.h[1] // 11000001-11010100-11000110-00011000
+// CHECK-INST: udot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x18,0xc6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4c618 <unknown>
+
+udot za.d[w10, 0], {z16.h - z19.h}, z4.h[1] // 11000001-11010100-11000110-00011000
+// CHECK-INST: udot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x18,0xc6,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4c618 <unknown>
+
+udot za.d[w8, 0, vgx4], {z12.h - z15.h}, z2.h[0] // 11000001-11010010-10000001-10011000
+// CHECK-INST: udot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]
+// CHECK-ENCODING: [0x98,0x81,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d28198 <unknown>
+
+udot za.d[w8, 0], {z12.h - z15.h}, z2.h[0] // 11000001-11010010-10000001-10011000
+// CHECK-INST: udot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]
+// CHECK-ENCODING: [0x98,0x81,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d28198 <unknown>
+
+udot za.d[w10, 1, vgx4], {z0.h - z3.h}, z10.h[0] // 11000001-11011010-11000000-00011001
+// CHECK-INST: udot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]
+// CHECK-ENCODING: [0x19,0xc0,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dac019 <unknown>
+
+udot za.d[w10, 1], {z0.h - z3.h}, z10.h[0] // 11000001-11011010-11000000-00011001
+// CHECK-INST: udot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]
+// CHECK-ENCODING: [0x19,0xc0,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dac019 <unknown>
+
+udot za.d[w8, 5, vgx4], {z20.h - z23.h}, z14.h[0] // 11000001-11011110-10000010-10011101
+// CHECK-INST: udot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]
+// CHECK-ENCODING: [0x9d,0x82,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de829d <unknown>
+
+udot za.d[w8, 5], {z20.h - z23.h}, z14.h[0] // 11000001-11011110-10000010-10011101
+// CHECK-INST: udot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]
+// CHECK-ENCODING: [0x9d,0x82,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de829d <unknown>
+
+udot za.d[w11, 2, vgx4], {z8.h - z11.h}, z1.h[1] // 11000001-11010001-11100101-00011010
+// CHECK-INST: udot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x1a,0xe5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1e51a <unknown>
+
+udot za.d[w11, 2], {z8.h - z11.h}, z1.h[1] // 11000001-11010001-11100101-00011010
+// CHECK-INST: udot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x1a,0xe5,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1e51a <unknown>
+
+udot za.d[w9, 7, vgx4], {z12.h - z15.h}, z11.h[0] // 11000001-11011011-10100001-10011111
+// CHECK-INST: udot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]
+// CHECK-ENCODING: [0x9f,0xa1,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dba19f <unknown>
+
+udot za.d[w9, 7], {z12.h - z15.h}, z11.h[0] // 11000001-11011011-10100001-10011111
+// CHECK-INST: udot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]
+// CHECK-ENCODING: [0x9f,0xa1,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dba19f <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/usdot-diagnostics.s b/llvm/test/MC/AArch64/SME2/usdot-diagnostics.s
new file mode 100644
index 0000000000000..dd55a19aa0523
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/usdot-diagnostics.s
@@ -0,0 +1,48 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid select register
+
+usdot za.s[w7, 0, vgx2], {z0.b-z1.b}, z0.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: usdot za.s[w7, 0, vgx2], {z0.b-z1.b}, z0.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+usdot za.s[w12, 0, vgx4], {z0.b-z3.b}, z0.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: usdot za.s[w12, 0, vgx4], {z0.b-z3.b}, z0.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid select offset
+
+usdot za.s[w8, 16], {z0.b-z1.b}, z0.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: usdot za.s[w8, 16], {z0.b-z1.b}, z0.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Out of range element index
+
+usdot za.s[w8, 0], {z0.b-z1.b}, z0.b[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: usdot za.s[w8, 0], {z0.b-z1.b}, z0.b[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+usdot za.s[w8, 0], {z0.b-z3.b}, z0.b[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: usdot za.s[w8, 0], {z0.b-z3.b}, z0.b[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// ZPR range constraint
+
+usdot za.s[w8, 5], {z0.b-z1.b}, z16.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: usdot za.s[w8, 5], {z0.b-z1.b}, z16.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+usdot za.s[w8, 5], {z0.b-z3.b}, z16.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: usdot za.s[w8, 5], {z0.b-z3.b}, z16.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/usdot.s b/llvm/test/MC/AArch64/SME2/usdot.s
new file mode 100644
index 0000000000000..2b05a7086bc06
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/usdot.s
@@ -0,0 +1,303 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+usdot za.s[w8, 0, vgx2], {z0.b, z1.b}, z0.b[0] // 11000001-01010000-00010000-00101000
+// CHECK-INST: usdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]
+// CHECK-ENCODING: [0x28,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501028 <unknown>
+
+usdot za.s[w8, 0], {z0.b, z1.b}, z0.b[0] // 11000001-01010000-00010000-00101000
+// CHECK-INST: usdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]
+// CHECK-ENCODING: [0x28,0x10,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501028 <unknown>
+
+usdot za.s[w10, 5, vgx2], {z10.b, z11.b}, z5.b[1] // 11000001-01010101-01010101-01101101
+// CHECK-INST: usdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x6d,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155556d <unknown>
+
+usdot za.s[w10, 5], {z10.b, z11.b}, z5.b[1] // 11000001-01010101-01010101-01101101
+// CHECK-INST: usdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x6d,0x55,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155556d <unknown>
+
+usdot za.s[w11, 7, vgx2], {z12.b, z13.b}, z8.b[3] // 11000001-01011000-01111101-10101111
+// CHECK-INST: usdot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]
+// CHECK-ENCODING: [0xaf,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587daf <unknown>
+
+usdot za.s[w11, 7], {z12.b, z13.b}, z8.b[3] // 11000001-01011000-01111101-10101111
+// CHECK-INST: usdot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]
+// CHECK-ENCODING: [0xaf,0x7d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1587daf <unknown>
+
+usdot za.s[w11, 7, vgx2], {z30.b, z31.b}, z15.b[3] // 11000001-01011111-01111111-11101111
+// CHECK-INST: usdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xef,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7fef <unknown>
+
+usdot za.s[w11, 7], {z30.b, z31.b}, z15.b[3] // 11000001-01011111-01111111-11101111
+// CHECK-INST: usdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xef,0x7f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f7fef <unknown>
+
+usdot za.s[w8, 5, vgx2], {z16.b, z17.b}, z0.b[3] // 11000001-01010000-00011110-00101101
+// CHECK-INST: usdot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]
+// CHECK-ENCODING: [0x2d,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e2d <unknown>
+
+usdot za.s[w8, 5], {z16.b, z17.b}, z0.b[3] // 11000001-01010000-00011110-00101101
+// CHECK-INST: usdot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]
+// CHECK-ENCODING: [0x2d,0x1e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1501e2d <unknown>
+
+usdot za.s[w8, 1, vgx2], {z0.b, z1.b}, z14.b[1] // 11000001-01011110-00010100-00101001
+// CHECK-INST: usdot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]
+// CHECK-ENCODING: [0x29,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1429 <unknown>
+
+usdot za.s[w8, 1], {z0.b, z1.b}, z14.b[1] // 11000001-01011110-00010100-00101001
+// CHECK-INST: usdot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]
+// CHECK-ENCODING: [0x29,0x14,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1429 <unknown>
+
+usdot za.s[w10, 0, vgx2], {z18.b, z19.b}, z4.b[1] // 11000001-01010100-01010110-01101000
+// CHECK-INST: usdot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x68,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545668 <unknown>
+
+usdot za.s[w10, 0], {z18.b, z19.b}, z4.b[1] // 11000001-01010100-01010110-01101000
+// CHECK-INST: usdot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x68,0x56,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1545668 <unknown>
+
+usdot za.s[w8, 0, vgx2], {z12.b, z13.b}, z2.b[2] // 11000001-01010010-00011001-10101000
+// CHECK-INST: usdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]
+// CHECK-ENCODING: [0xa8,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15219a8 <unknown>
+
+usdot za.s[w8, 0], {z12.b, z13.b}, z2.b[2] // 11000001-01010010-00011001-10101000
+// CHECK-INST: usdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]
+// CHECK-ENCODING: [0xa8,0x19,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15219a8 <unknown>
+
+usdot za.s[w10, 1, vgx2], {z0.b, z1.b}, z10.b[2] // 11000001-01011010-01011000-00101001
+// CHECK-INST: usdot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]
+// CHECK-ENCODING: [0x29,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5829 <unknown>
+
+usdot za.s[w10, 1], {z0.b, z1.b}, z10.b[2] // 11000001-01011010-01011000-00101001
+// CHECK-INST: usdot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]
+// CHECK-ENCODING: [0x29,0x58,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a5829 <unknown>
+
+usdot za.s[w8, 5, vgx2], {z22.b, z23.b}, z14.b[2] // 11000001-01011110-00011010-11101101
+// CHECK-INST: usdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xed,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1aed <unknown>
+
+usdot za.s[w8, 5], {z22.b, z23.b}, z14.b[2] // 11000001-01011110-00011010-11101101
+// CHECK-INST: usdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xed,0x1a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e1aed <unknown>
+
+usdot za.s[w11, 2, vgx2], {z8.b, z9.b}, z1.b[1] // 11000001-01010001-01110101-00101010
+// CHECK-INST: usdot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]
+// CHECK-ENCODING: [0x2a,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151752a <unknown>
+
+usdot za.s[w11, 2], {z8.b, z9.b}, z1.b[1] // 11000001-01010001-01110101-00101010
+// CHECK-INST: usdot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]
+// CHECK-ENCODING: [0x2a,0x75,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151752a <unknown>
+
+usdot za.s[w9, 7, vgx2], {z12.b, z13.b}, z11.b[2] // 11000001-01011011-00111001-10101111
+// CHECK-INST: usdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]
+// CHECK-ENCODING: [0xaf,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b39af <unknown>
+
+usdot za.s[w9, 7], {z12.b, z13.b}, z11.b[2] // 11000001-01011011-00111001-10101111
+// CHECK-INST: usdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]
+// CHECK-ENCODING: [0xaf,0x39,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b39af <unknown>
+
+
+usdot za.s[w8, 0, vgx4], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10010000-00101000
+// CHECK-INST: usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+// CHECK-ENCODING: [0x28,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509028 <unknown>
+
+usdot za.s[w8, 0], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10010000-00101000
+// CHECK-INST: usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+// CHECK-ENCODING: [0x28,0x90,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509028 <unknown>
+
+usdot za.s[w10, 5, vgx4], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11010101-00101101
+// CHECK-INST: usdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x2d,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d52d <unknown>
+
+usdot za.s[w10, 5], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11010101-00101101
+// CHECK-INST: usdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x2d,0xd5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155d52d <unknown>
+
+usdot za.s[w11, 7, vgx4], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11111101-10101111
+// CHECK-INST: usdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
+// CHECK-ENCODING: [0xaf,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fdaf <unknown>
+
+usdot za.s[w11, 7], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11111101-10101111
+// CHECK-INST: usdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
+// CHECK-ENCODING: [0xaf,0xfd,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158fdaf <unknown>
+
+usdot za.s[w11, 7, vgx4], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11111111-10101111
+// CHECK-INST: usdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xaf,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fffaf <unknown>
+
+usdot za.s[w11, 7], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11111111-10101111
+// CHECK-INST: usdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xaf,0xff,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fffaf <unknown>
+
+usdot za.s[w8, 5, vgx4], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10011110-00101101
+// CHECK-INST: usdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
+// CHECK-ENCODING: [0x2d,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e2d <unknown>
+
+usdot za.s[w8, 5], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10011110-00101101
+// CHECK-INST: usdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
+// CHECK-ENCODING: [0x2d,0x9e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1509e2d <unknown>
+
+usdot za.s[w8, 1, vgx4], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10010100-00101001
+// CHECK-INST: usdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
+// CHECK-ENCODING: [0x29,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9429 <unknown>
+
+usdot za.s[w8, 1], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10010100-00101001
+// CHECK-INST: usdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
+// CHECK-ENCODING: [0x29,0x94,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9429 <unknown>
+
+usdot za.s[w10, 0, vgx4], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11010110-00101000
+// CHECK-INST: usdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x28,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d628 <unknown>
+
+usdot za.s[w10, 0], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11010110-00101000
+// CHECK-INST: usdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x28,0xd6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154d628 <unknown>
+
+usdot za.s[w8, 0, vgx4], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10011001-10101000
+// CHECK-INST: usdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
+// CHECK-ENCODING: [0xa8,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15299a8 <unknown>
+
+usdot za.s[w8, 0], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10011001-10101000
+// CHECK-INST: usdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
+// CHECK-ENCODING: [0xa8,0x99,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15299a8 <unknown>
+
+usdot za.s[w10, 1, vgx4], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11011000-00101001
+// CHECK-INST: usdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
+// CHECK-ENCODING: [0x29,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad829 <unknown>
+
+usdot za.s[w10, 1], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11011000-00101001
+// CHECK-INST: usdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
+// CHECK-ENCODING: [0x29,0xd8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ad829 <unknown>
+
+usdot za.s[w8, 5, vgx4], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10011010-10101101
+// CHECK-INST: usdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xad,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9aad <unknown>
+
+usdot za.s[w8, 5], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10011010-10101101
+// CHECK-INST: usdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xad,0x9a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e9aad <unknown>
+
+usdot za.s[w11, 2, vgx4], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11110101-00101010
+// CHECK-INST: usdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
+// CHECK-ENCODING: [0x2a,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f52a <unknown>
+
+usdot za.s[w11, 2], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11110101-00101010
+// CHECK-INST: usdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
+// CHECK-ENCODING: [0x2a,0xf5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151f52a <unknown>
+
+usdot za.s[w9, 7, vgx4], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10111001-10101111
+// CHECK-INST: usdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
+// CHECK-ENCODING: [0xaf,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb9af <unknown>
+
+usdot za.s[w9, 7], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10111001-10101111
+// CHECK-INST: usdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
+// CHECK-ENCODING: [0xaf,0xb9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15bb9af <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/uvdot-diagnostics.s b/llvm/test/MC/AArch64/SME2/uvdot-diagnostics.s
new file mode 100644
index 0000000000000..dd990cbd68c08
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/uvdot-diagnostics.s
@@ -0,0 +1,69 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Out of range index offset
+
+uvdot za.s[w8, 8, vgx4], {z0.b-z3.b}, z0.b[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: uvdot za.s[w8, 8, vgx4], {z0.b-z3.b}, z0.b[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uvdot za.s[w8, -1, vgx2], {z0.b-z1.b}, z0.b[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: uvdot za.s[w8, -1, vgx2], {z0.b-z1.b}, z0.b[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+uvdot za.s[w7, 7, vgx2], {z0.h-z1.h}, z0.h[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: uvdot za.s[w7, 7, vgx2], {z0.h-z1.h}, z0.h[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uvdot za.d[w12, 7, vgx4], {z0.h-z3.h}, z0.h[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: uvdot za.d[w12, 7, vgx4], {z0.h-z3.h}, z0.h[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+uvdot za.d[w8, 0, vgx4], {z0.h-z4.h}, z0.h[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: uvdot za.d[w8, 0, vgx4], {z0.h-z4.h}, z0.h[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uvdot za.s[w8, 0, vgx4], {z1.b-z4.b}, z0.b[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element type
+// CHECK-NEXT: uvdot za.s[w8, 0, vgx4], {z1.b-z4.b}, z0.b[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Matrix Operand
+
+uvdot za.b[w8, 0, vgx4], {z0.h-z3.h}, z4.h[7]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
+// CHECK-NEXT: uvdot za.b[w8, 0, vgx4], {z0.h-z3.h}, z4.h[7]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector grouping
+
+uvdot za.s[w8, 0, vgx2], {z0.b-z3.b}, z14.b[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uvdot za.s[w8, 0, vgx2], {z0.b-z3.b}, z14.b[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid lane index
+
+uvdot za.s[w11, 7], {z30.h-z31.h}, z15.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]
+// CHECK-NEXT: uvdot za.s[w11, 7], {z30.h-z31.h}, z15.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uvdot za.s[w11, 7], {z30.h-z31.h}, z15.h[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]
+// CHECK-NEXT: za.s[w11, 7], {z30.h-z31.h}, z15.h[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/uvdot.s b/llvm/test/MC/AArch64/SME2/uvdot.s
new file mode 100644
index 0000000000000..9f93b5b3ab9c0
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/uvdot.s
@@ -0,0 +1,448 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2,+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+sme-i16i64 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+uvdot za.s[w8, 0, vgx2], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00000000-00110000
+// CHECK-INST: uvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x30,0x00,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500030 <unknown>
+
+uvdot za.s[w8, 0], {z0.h, z1.h}, z0.h[0] // 11000001-01010000-00000000-00110000
+// CHECK-INST: uvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+// CHECK-ENCODING: [0x30,0x00,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500030 <unknown>
+
+uvdot za.s[w10, 5, vgx2], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01000101-01110101
+// CHECK-INST: uvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x75,0x45,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1554575 <unknown>
+
+uvdot za.s[w10, 5], {z10.h, z11.h}, z5.h[1] // 11000001-01010101-01000101-01110101
+// CHECK-INST: uvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x75,0x45,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1554575 <unknown>
+
+uvdot za.s[w11, 7, vgx2], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01101101-10110111
+// CHECK-INST: uvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0xb7,0x6d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1586db7 <unknown>
+
+uvdot za.s[w11, 7], {z12.h, z13.h}, z8.h[3] // 11000001-01011000-01101101-10110111
+// CHECK-INST: uvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]
+// CHECK-ENCODING: [0xb7,0x6d,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1586db7 <unknown>
+
+uvdot za.s[w11, 7, vgx2], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01101111-11110111
+// CHECK-INST: uvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xf7,0x6f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f6ff7 <unknown>
+
+uvdot za.s[w11, 7], {z30.h, z31.h}, z15.h[3] // 11000001-01011111-01101111-11110111
+// CHECK-INST: uvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]
+// CHECK-ENCODING: [0xf7,0x6f,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15f6ff7 <unknown>
+
+uvdot za.s[w8, 5, vgx2], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00001110-00110101
+// CHECK-INST: uvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x35,0x0e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500e35 <unknown>
+
+uvdot za.s[w8, 5], {z16.h, z17.h}, z0.h[3] // 11000001-01010000-00001110-00110101
+// CHECK-INST: uvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]
+// CHECK-ENCODING: [0x35,0x0e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1500e35 <unknown>
+
+uvdot za.s[w8, 1, vgx2], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00000100-00110001
+// CHECK-INST: uvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x31,0x04,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0431 <unknown>
+
+uvdot za.s[w8, 1], {z0.h, z1.h}, z14.h[1] // 11000001-01011110-00000100-00110001
+// CHECK-INST: uvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]
+// CHECK-ENCODING: [0x31,0x04,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0431 <unknown>
+
+uvdot za.s[w10, 0, vgx2], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01000110-01110000
+// CHECK-INST: uvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x70,0x46,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1544670 <unknown>
+
+uvdot za.s[w10, 0], {z18.h, z19.h}, z4.h[1] // 11000001-01010100-01000110-01110000
+// CHECK-INST: uvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x70,0x46,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1544670 <unknown>
+
+uvdot za.s[w8, 0, vgx2], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00001001-10110000
+// CHECK-INST: uvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0xb0,0x09,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15209b0 <unknown>
+
+uvdot za.s[w8, 0], {z12.h, z13.h}, z2.h[2] // 11000001-01010010-00001001-10110000
+// CHECK-INST: uvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]
+// CHECK-ENCODING: [0xb0,0x09,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15209b0 <unknown>
+
+uvdot za.s[w10, 1, vgx2], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01001000-00110001
+// CHECK-INST: uvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x31,0x48,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a4831 <unknown>
+
+uvdot za.s[w10, 1], {z0.h, z1.h}, z10.h[2] // 11000001-01011010-01001000-00110001
+// CHECK-INST: uvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]
+// CHECK-ENCODING: [0x31,0x48,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15a4831 <unknown>
+
+uvdot za.s[w8, 5, vgx2], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00001010-11110101
+// CHECK-INST: uvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xf5,0x0a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0af5 <unknown>
+
+uvdot za.s[w8, 5], {z22.h, z23.h}, z14.h[2] // 11000001-01011110-00001010-11110101
+// CHECK-INST: uvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]
+// CHECK-ENCODING: [0xf5,0x0a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e0af5 <unknown>
+
+uvdot za.s[w11, 2, vgx2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01100101-00110010
+// CHECK-INST: uvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x32,0x65,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1516532 <unknown>
+
+uvdot za.s[w11, 2], {z8.h, z9.h}, z1.h[1] // 11000001-01010001-01100101-00110010
+// CHECK-INST: uvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]
+// CHECK-ENCODING: [0x32,0x65,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1516532 <unknown>
+
+uvdot za.s[w9, 7, vgx2], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00101001-10110111
+// CHECK-INST: uvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0xb7,0x29,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b29b7 <unknown>
+
+uvdot za.s[w9, 7], {z12.h, z13.h}, z11.h[2] // 11000001-01011011-00101001-10110111
+// CHECK-INST: uvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]
+// CHECK-ENCODING: [0xb7,0x29,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15b29b7 <unknown>
+
+
+uvdot za.s[w8, 0, vgx4], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10000000-00110000
+// CHECK-INST: uvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+// CHECK-ENCODING: [0x30,0x80,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508030 <unknown>
+
+uvdot za.s[w8, 0], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10000000-00110000
+// CHECK-INST: uvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+// CHECK-ENCODING: [0x30,0x80,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508030 <unknown>
+
+uvdot za.s[w10, 5, vgx4], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11000101-00110101
+// CHECK-INST: uvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x35,0xc5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155c535 <unknown>
+
+uvdot za.s[w10, 5], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11000101-00110101
+// CHECK-INST: uvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
+// CHECK-ENCODING: [0x35,0xc5,0x55,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c155c535 <unknown>
+
+uvdot za.s[w11, 7, vgx4], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11101101-10110111
+// CHECK-INST: uvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
+// CHECK-ENCODING: [0xb7,0xed,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158edb7 <unknown>
+
+uvdot za.s[w11, 7], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11101101-10110111
+// CHECK-INST: uvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
+// CHECK-ENCODING: [0xb7,0xed,0x58,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c158edb7 <unknown>
+
+uvdot za.s[w11, 7, vgx4], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11101111-10110111
+// CHECK-INST: uvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xb7,0xef,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fefb7 <unknown>
+
+uvdot za.s[w11, 7], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11101111-10110111
+// CHECK-INST: uvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
+// CHECK-ENCODING: [0xb7,0xef,0x5f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15fefb7 <unknown>
+
+uvdot za.s[w8, 5, vgx4], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10001110-00110101
+// CHECK-INST: uvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
+// CHECK-ENCODING: [0x35,0x8e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508e35 <unknown>
+
+uvdot za.s[w8, 5], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10001110-00110101
+// CHECK-INST: uvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
+// CHECK-ENCODING: [0x35,0x8e,0x50,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1508e35 <unknown>
+
+uvdot za.s[w8, 1, vgx4], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10000100-00110001
+// CHECK-INST: uvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
+// CHECK-ENCODING: [0x31,0x84,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8431 <unknown>
+
+uvdot za.s[w8, 1], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10000100-00110001
+// CHECK-INST: uvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
+// CHECK-ENCODING: [0x31,0x84,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8431 <unknown>
+
+uvdot za.s[w10, 0, vgx4], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11000110-00110000
+// CHECK-INST: uvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x30,0xc6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154c630 <unknown>
+
+uvdot za.s[w10, 0], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11000110-00110000
+// CHECK-INST: uvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
+// CHECK-ENCODING: [0x30,0xc6,0x54,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c154c630 <unknown>
+
+uvdot za.s[w8, 0, vgx4], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10001001-10110000
+// CHECK-INST: uvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
+// CHECK-ENCODING: [0xb0,0x89,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15289b0 <unknown>
+
+uvdot za.s[w8, 0], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10001001-10110000
+// CHECK-INST: uvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
+// CHECK-ENCODING: [0xb0,0x89,0x52,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15289b0 <unknown>
+
+uvdot za.s[w10, 1, vgx4], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11001000-00110001
+// CHECK-INST: uvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
+// CHECK-ENCODING: [0x31,0xc8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ac831 <unknown>
+
+uvdot za.s[w10, 1], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11001000-00110001
+// CHECK-INST: uvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
+// CHECK-ENCODING: [0x31,0xc8,0x5a,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ac831 <unknown>
+
+uvdot za.s[w8, 5, vgx4], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10001010-10110101
+// CHECK-INST: uvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xb5,0x8a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8ab5 <unknown>
+
+uvdot za.s[w8, 5], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10001010-10110101
+// CHECK-INST: uvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
+// CHECK-ENCODING: [0xb5,0x8a,0x5e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15e8ab5 <unknown>
+
+uvdot za.s[w11, 2, vgx4], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11100101-00110010
+// CHECK-INST: uvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
+// CHECK-ENCODING: [0x32,0xe5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151e532 <unknown>
+
+uvdot za.s[w11, 2], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11100101-00110010
+// CHECK-INST: uvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
+// CHECK-ENCODING: [0x32,0xe5,0x51,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c151e532 <unknown>
+
+uvdot za.s[w9, 7, vgx4], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10101001-10110111
+// CHECK-INST: uvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
+// CHECK-ENCODING: [0xb7,0xa9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ba9b7 <unknown>
+
+uvdot za.s[w9, 7], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10101001-10110111
+// CHECK-INST: uvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
+// CHECK-ENCODING: [0xb7,0xa9,0x5b,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c15ba9b7 <unknown>
+
+
+uvdot za.d[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0] // 11000001-11010000-10001000-00011000
+// CHECK-INST: uvdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x88,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08818 <unknown>
+
+uvdot za.d[w8, 0], {z0.h - z3.h}, z0.h[0] // 11000001-11010000-10001000-00011000
+// CHECK-INST: uvdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+// CHECK-ENCODING: [0x18,0x88,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08818 <unknown>
+
+uvdot za.d[w10, 5, vgx4], {z8.h - z11.h}, z5.h[1] // 11000001-11010101-11001101-00011101
+// CHECK-INST: uvdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x1d,0xcd,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5cd1d <unknown>
+
+uvdot za.d[w10, 5], {z8.h - z11.h}, z5.h[1] // 11000001-11010101-11001101-00011101
+// CHECK-INST: uvdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]
+// CHECK-ENCODING: [0x1d,0xcd,0xd5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d5cd1d <unknown>
+
+uvdot za.d[w11, 7, vgx4], {z12.h - z15.h}, z8.h[1] // 11000001-11011000-11101101-10011111
+// CHECK-INST: uvdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]
+// CHECK-ENCODING: [0x9f,0xed,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8ed9f <unknown>
+
+uvdot za.d[w11, 7], {z12.h - z15.h}, z8.h[1] // 11000001-11011000-11101101-10011111
+// CHECK-INST: uvdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]
+// CHECK-ENCODING: [0x9f,0xed,0xd8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d8ed9f <unknown>
+
+uvdot za.d[w11, 7, vgx4], {z28.h - z31.h}, z15.h[1] // 11000001-11011111-11101111-10011111
+// CHECK-INST: uvdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]
+// CHECK-ENCODING: [0x9f,0xef,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfef9f <unknown>
+
+uvdot za.d[w11, 7], {z28.h - z31.h}, z15.h[1] // 11000001-11011111-11101111-10011111
+// CHECK-INST: uvdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]
+// CHECK-ENCODING: [0x9f,0xef,0xdf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dfef9f <unknown>
+
+uvdot za.d[w8, 5, vgx4], {z16.h - z19.h}, z0.h[1] // 11000001-11010000-10001110-00011101
+// CHECK-INST: uvdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]
+// CHECK-ENCODING: [0x1d,0x8e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08e1d <unknown>
+
+uvdot za.d[w8, 5], {z16.h - z19.h}, z0.h[1] // 11000001-11010000-10001110-00011101
+// CHECK-INST: uvdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]
+// CHECK-ENCODING: [0x1d,0x8e,0xd0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d08e1d <unknown>
+
+uvdot za.d[w8, 1, vgx4], {z0.h - z3.h}, z14.h[1] // 11000001-11011110-10001100-00011001
+// CHECK-INST: uvdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x19,0x8c,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8c19 <unknown>
+
+uvdot za.d[w8, 1], {z0.h - z3.h}, z14.h[1] // 11000001-11011110-10001100-00011001
+// CHECK-INST: uvdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]
+// CHECK-ENCODING: [0x19,0x8c,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8c19 <unknown>
+
+uvdot za.d[w10, 0, vgx4], {z16.h - z19.h}, z4.h[1] // 11000001-11010100-11001110-00011000
+// CHECK-INST: uvdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x18,0xce,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4ce18 <unknown>
+
+uvdot za.d[w10, 0], {z16.h - z19.h}, z4.h[1] // 11000001-11010100-11001110-00011000
+// CHECK-INST: uvdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]
+// CHECK-ENCODING: [0x18,0xce,0xd4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d4ce18 <unknown>
+
+uvdot za.d[w8, 0, vgx4], {z12.h - z15.h}, z2.h[0] // 11000001-11010010-10001001-10011000
+// CHECK-INST: uvdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]
+// CHECK-ENCODING: [0x98,0x89,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d28998 <unknown>
+
+uvdot za.d[w8, 0], {z12.h - z15.h}, z2.h[0] // 11000001-11010010-10001001-10011000
+// CHECK-INST: uvdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]
+// CHECK-ENCODING: [0x98,0x89,0xd2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d28998 <unknown>
+
+uvdot za.d[w10, 1, vgx4], {z0.h - z3.h}, z10.h[0] // 11000001-11011010-11001000-00011001
+// CHECK-INST: uvdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]
+// CHECK-ENCODING: [0x19,0xc8,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dac819 <unknown>
+
+uvdot za.d[w10, 1], {z0.h - z3.h}, z10.h[0] // 11000001-11011010-11001000-00011001
+// CHECK-INST: uvdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]
+// CHECK-ENCODING: [0x19,0xc8,0xda,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dac819 <unknown>
+
+uvdot za.d[w8, 5, vgx4], {z20.h - z23.h}, z14.h[0] // 11000001-11011110-10001010-10011101
+// CHECK-INST: uvdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]
+// CHECK-ENCODING: [0x9d,0x8a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8a9d <unknown>
+
+uvdot za.d[w8, 5], {z20.h - z23.h}, z14.h[0] // 11000001-11011110-10001010-10011101
+// CHECK-INST: uvdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]
+// CHECK-ENCODING: [0x9d,0x8a,0xde,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1de8a9d <unknown>
+
+uvdot za.d[w11, 2, vgx4], {z8.h - z11.h}, z1.h[1] // 11000001-11010001-11101101-00011010
+// CHECK-INST: uvdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x1a,0xed,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1ed1a <unknown>
+
+uvdot za.d[w11, 2], {z8.h - z11.h}, z1.h[1] // 11000001-11010001-11101101-00011010
+// CHECK-INST: uvdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]
+// CHECK-ENCODING: [0x1a,0xed,0xd1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1d1ed1a <unknown>
+
+uvdot za.d[w9, 7, vgx4], {z12.h - z15.h}, z11.h[0] // 11000001-11011011-10101001-10011111
+// CHECK-INST: uvdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]
+// CHECK-ENCODING: [0x9f,0xa9,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dba99f <unknown>
+
+uvdot za.d[w9, 7], {z12.h - z15.h}, z11.h[0] // 11000001-11011011-10101001-10011111
+// CHECK-INST: uvdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]
+// CHECK-ENCODING: [0x9f,0xa9,0xdb,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1dba99f <unknown>
+
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