[PATCH] D136463: [SWP] Recognize mem carried dep with different base

[Brendon Cahoon via Phabricator via llvm-commits]

bcahoon added inline comments.


================
Comment at: llvm/lib/CodeGen/MachinePipeliner.cpp:2301
   int D = 0;
-  if (!LoopDef || !TII->getIncrementValue(*LoopDef, D))
+  if (!LoopDefS || !TII->getIncrementValue(*LoopDefS, D))
     return true;
----------------
I don't think this is needed because computeDelta performs this check. However, this isn't really related to your change...


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Comment at: llvm/test/CodeGen/Hexagon/swp-carried-dep3.mir:14
+# CHECK-NEXT: SU(5)
+# CHECK-NEXT: SU(7)
+
----------------
It looks like this is the same output without your patch. Can you add a test, or change this one, that shows the effect of the patch?


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Comment at: llvm/test/CodeGen/Hexagon/swp-carried-dep3.mir:52
+    %18:intregs, %10:intregs = L2_loadrh_pi %3, 2 :: (load (s16))
+    %19:intregs = L2_loadrh_io %21, -8 :: (load (s16))
+    %20:intregs = A2_addi %18, 10
----------------
If the offset is changed from -8 to 0, then there is no loop carried dependence with your patch.

BTW, if you want to use post-increment instructions it would be
 %19:intregs, %22:intregs = L2_loadrh_pi %21, 2 :: (load (s16))


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Comment at: llvm/test/CodeGen/Hexagon/swp-carried-dep3.mir:54
+    %20:intregs = A2_addi %18, 10
+    S2_storerh_io %4, 0, killed %20 :: (store (s16))
+    %7:intregs = M2_acci %19, %6, %18
----------------
The post-increment version is
%9:intregs = S2_storerh_pi %4, 2, killed %20 :: (store (s16))


Repository:
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  https://reviews.llvm.org/D136463/new/

https://reviews.llvm.org/D136463