[PATCH] D136463: [SWP] Recognize mem carried dep with different base

[Thomas Preud'homme via Phabricator via llvm-commits]

thopre added inline comments.


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Comment at: llvm/test/CodeGen/Hexagon/swp-carried-dep3.mir:57
+    %9:intregs = A2_addi %4, 4
+    %22:intregs = A2_addi %21, 4
+    ENDLOOP0 %bb.2, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
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The loadrh_io + this A2_addi is meant to represent a postinc MIR load. Likewise for the S2_storeh_io and the A2_addi on the line before. This is the usecase we are facing on the Graphcore IPU.

If there's a way to reproduce the same either on Hexagon or PowerPC I'm happy to amend the testcase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136463/new/

https://reviews.llvm.org/D136463