[llvm] 656e53e - [instcombine] Add basic test coverage for demanded bits of scalable vectors
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 21 08:00:03 PDT 2022
Author: Philip Reames
Date: 2022-10-21T07:59:04-07:00
New Revision: 656e53e544e9bc8eded5906094d97611ff87ca47
URL: https://github.com/llvm/llvm-project/commit/656e53e544e9bc8eded5906094d97611ff87ca47
DIFF: https://github.com/llvm/llvm-project/commit/656e53e544e9bc8eded5906094d97611ff87ca47.diff
LOG: [instcombine] Add basic test coverage for demanded bits of scalable vectors
Added:
Modified:
llvm/test/Transforms/InstCombine/add.ll
llvm/test/Transforms/InstCombine/intrinsics.ll
llvm/test/Transforms/InstCombine/mul-masked-bits.ll
llvm/test/Transforms/InstCombine/shift.ll
llvm/test/Transforms/InstCombine/udiv-simplify.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll
index ccb18f935411..b5e7746bdcf3 100644
--- a/llvm/test/Transforms/InstCombine/add.ll
+++ b/llvm/test/Transforms/InstCombine/add.ll
@@ -2334,3 +2334,14 @@ define i8 @mul_not_negpow2(i8 %x) {
%a = add i8 %m, 42
ret i8 %a
}
+
+define <vscale x 1 x i32> @add_to_or_scalable(<vscale x 1 x i32> %in) {
+; CHECK-LABEL: @add_to_or_scalable(
+; CHECK-NEXT: [[SHL:%.*]] = shl <vscale x 1 x i32> [[IN:%.*]], shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 1, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[ADD:%.*]] = add <vscale x 1 x i32> [[SHL]], shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 1, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: ret <vscale x 1 x i32> [[ADD]]
+;
+ %shl = shl <vscale x 1 x i32> %in, shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 1, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
+ %add = add <vscale x 1 x i32> %shl, shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 1, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
+ ret <vscale x 1 x i32> %add
+}
diff --git a/llvm/test/Transforms/InstCombine/intrinsics.ll b/llvm/test/Transforms/InstCombine/intrinsics.ll
index 68c307b47eb8..143136e3c77a 100644
--- a/llvm/test/Transforms/InstCombine/intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/intrinsics.ll
@@ -22,6 +22,7 @@ declare double @llvm.ceil.f64(double %Val) nounwind readonly
declare double @llvm.trunc.f64(double %Val) nounwind readonly
declare double @llvm.rint.f64(double %Val) nounwind readonly
declare double @llvm.nearbyint.f64(double %Val) nounwind readonly
+declare <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32>, i1) nounwind readnone
define void @powi(double %V, ptr %P) {
; CHECK-LABEL: @powi(
@@ -124,6 +125,19 @@ define <2 x i1> @cttz_knownbits_vec(<2 x i32> %arg) {
ret <2 x i1> %res
}
+define <vscale x 1 x i1> @cttz_knownbits_scalable_vec(<vscale x 1 x i32> %arg) {
+; CHECK-LABEL: @cttz_knownbits_scalable_vec(
+; CHECK-NEXT: [[OR:%.*]] = and <vscale x 1 x i32> [[ARG:%.*]], shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 27, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[RES:%.*]] = icmp eq <vscale x 1 x i32> [[OR]], shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 20, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: ret <vscale x 1 x i1> [[RES]]
+;
+ %or = or <vscale x 1 x i32> %arg, shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 4, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
+ %cnt = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %or, i1 true) nounwind readnone
+ %res = icmp eq <vscale x 1 x i32> %cnt, shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 4, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
+ ret <vscale x 1 x i1> %res
+}
+
+
define i32 @cttz_knownbits2(i32 %arg) {
; CHECK-LABEL: @cttz_knownbits2(
; CHECK-NEXT: [[OR:%.*]] = or i32 [[ARG:%.*]], 4
@@ -490,5 +504,3 @@ define void @nearbyint(ptr %P) {
ret void
}
-; CHECK: [[RNG0]] = !{i32 0, i32 3}
-; CHECK: [[RNG1]] = !{i8 0, i8 3}
diff --git a/llvm/test/Transforms/InstCombine/mul-masked-bits.ll b/llvm/test/Transforms/InstCombine/mul-masked-bits.ll
index 644556c55c85..9122bf08a34e 100644
--- a/llvm/test/Transforms/InstCombine/mul-masked-bits.ll
+++ b/llvm/test/Transforms/InstCombine/mul-masked-bits.ll
@@ -78,6 +78,19 @@ define <4 x i32> @combine_mul_self_demandedbits_vector(<4 x i32> %x) {
ret <4 x i32> %3
}
+define <vscale x 2 x i32> @combine_mul_self_demandedbits_vector2(<vscale x 2 x i32> %x) {
+; CHECK-LABEL: @combine_mul_self_demandedbits_vector2(
+; CHECK-NEXT: [[TMP1:%.*]] = freeze <vscale x 2 x i32> [[X:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = mul <vscale x 2 x i32> [[TMP1]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = and <vscale x 2 x i32> [[TMP2]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 -3, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
+; CHECK-NEXT: ret <vscale x 2 x i32> [[TMP3]]
+;
+ %1 = freeze <vscale x 2 x i32> %x
+ %2 = mul <vscale x 2 x i32> %1, %1
+ %3 = and <vscale x 2 x i32> %2, shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 -3, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
+ ret <vscale x 2 x i32> %3
+}
+
define i8 @one_demanded_bit(i8 %x) {
; CHECK-LABEL: @one_demanded_bit(
; CHECK-NEXT: [[M:%.*]] = shl i8 [[X:%.*]], 6
diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll
index 64e98b88f7cc..0a97efb225a6 100644
--- a/llvm/test/Transforms/InstCombine/shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift.ll
@@ -1358,6 +1358,16 @@ define <2 x i8> @ashr_demanded_bits_splat(<2 x i8> %x) {
ret <2 x i8> %shr
}
+define <vscale x 8 x i8> @ashr_demanded_bits_splat2(<vscale x 8 x i8> %x) {
+; CHECK-LABEL: @ashr_demanded_bits_splat2(
+; CHECK-NEXT: [[AND:%.*]] = ashr <vscale x 8 x i8> [[X:%.*]], shufflevector (<vscale x 8 x i8> insertelement (<vscale x 8 x i8> poison, i8 7, i32 0), <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer)
+; CHECK-NEXT: ret <vscale x 8 x i8> [[AND]]
+;
+ %and = and <vscale x 8 x i8> %x, shufflevector (<vscale x 8 x i8> insertelement (<vscale x 8 x i8> poison, i8 128, i32 0), <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer)
+ %shr = ashr <vscale x 8 x i8> %and, shufflevector (<vscale x 8 x i8> insertelement (<vscale x 8 x i8> poison, i8 7, i32 0), <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer)
+ ret <vscale x 8 x i8> %shr
+}
+
define <2 x i8> @lshr_demanded_bits_splat(<2 x i8> %x) {
; CHECK-LABEL: @lshr_demanded_bits_splat(
; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 7, i8 7>
@@ -1368,6 +1378,16 @@ define <2 x i8> @lshr_demanded_bits_splat(<2 x i8> %x) {
ret <2 x i8> %shr
}
+define <vscale x 8 x i8> @lshr_demanded_bits_splat2(<vscale x 8 x i8> %x) {
+; CHECK-LABEL: @lshr_demanded_bits_splat2(
+; CHECK-NEXT: [[AND:%.*]] = lshr <vscale x 8 x i8> [[X:%.*]], shufflevector (<vscale x 8 x i8> insertelement (<vscale x 8 x i8> poison, i8 7, i32 0), <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer)
+; CHECK-NEXT: ret <vscale x 8 x i8> [[AND]]
+;
+ %and = and <vscale x 8 x i8> %x, shufflevector (<vscale x 8 x i8> insertelement (<vscale x 8 x i8> poison, i8 128, i32 0), <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer)
+ %shr = lshr <vscale x 8 x i8> %and, shufflevector (<vscale x 8 x i8> insertelement (<vscale x 8 x i8> poison, i8 7, i32 0), <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer)
+ ret <vscale x 8 x i8> %shr
+}
+
; Make sure known bits works correctly with non power of 2 bit widths.
define i7 @test65(i7 %a, i7 %b) {
; CHECK-LABEL: @test65(
diff --git a/llvm/test/Transforms/InstCombine/udiv-simplify.ll b/llvm/test/Transforms/InstCombine/udiv-simplify.ll
index a01b4a2ecbc8..9e5b02f5d3ad 100644
--- a/llvm/test/Transforms/InstCombine/udiv-simplify.ll
+++ b/llvm/test/Transforms/InstCombine/udiv-simplify.ll
@@ -55,8 +55,8 @@ define i64 @test2_PR2274(i32 %x, i32 %v) nounwind {
define i32 @PR30366(i1 %a) {
; CHECK-LABEL: @PR30366(
; CHECK-NEXT: [[Z:%.*]] = zext i1 [[A:%.*]] to i32
-; CHECK-NEXT: [[D:%.*]] = lshr i32 [[Z]], zext (i16 ptrtoint (ptr @b to i16) to i32)
-; CHECK-NEXT: ret i32 [[D]]
+; CHECK-NEXT: [[D1:%.*]] = lshr i32 [[Z]], zext (i16 ptrtoint (ptr @b to i16) to i32)
+; CHECK-NEXT: ret i32 [[D1]]
;
%z = zext i1 %a to i32
%d = udiv i32 %z, zext (i16 shl (i16 1, i16 ptrtoint (ptr @b to i16)) to i32)
@@ -103,3 +103,14 @@ define i32 @udiv_exact_demanded(i32 %a) {
%u = udiv exact i32 %o, 12
ret i32 %u
}
+
+define <vscale x 1 x i32> @udiv_demanded3(<vscale x 1 x i32> %a) {
+; CHECK-LABEL: @udiv_demanded3(
+; CHECK-NEXT: [[O:%.*]] = or <vscale x 1 x i32> [[A:%.*]], shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 3, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: [[U:%.*]] = udiv <vscale x 1 x i32> [[O]], shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 12, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
+; CHECK-NEXT: ret <vscale x 1 x i32> [[U]]
+;
+ %o = or <vscale x 1 x i32> %a, shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 3, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
+ %u = udiv <vscale x 1 x i32> %o, shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 12, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
+ ret <vscale x 1 x i32> %u
+}
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