[llvm] d3c8aa7 - [AArch64]SME2 Multi-vector-Multiple Vectors SQDMULH instructions
Caroline Concatto via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 21 07:36:41 PDT 2022
Author: Caroline Concatto
Date: 2022-10-21T15:36:13+01:00
New Revision: d3c8aa7a43a9a58403750584fa9694cf97ceb063
URL: https://github.com/llvm/llvm-project/commit/d3c8aa7a43a9a58403750584fa9694cf97ceb063
DIFF: https://github.com/llvm/llvm-project/commit/d3c8aa7a43a9a58403750584fa9694cf97ceb063.diff
LOG: [AArch64]SME2 Multi-vector-Multiple Vectors SQDMULH instructions
This patch adds the assembly/disassembly for the following instruction:
SQDMULH (multiple vectors): Multi-vector signed saturating doubling multiply high.
For 2 and 4 ZA registers
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/SME-Instructions/SQDMULH--multiple-vectors---Multi-vector-signed-saturating-doubling-multiply-high-?lang=en
Depends on: D135563
Differential Revision: https://reviews.llvm.org/D135575
Added:
Modified:
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
llvm/lib/Target/AArch64/SMEInstrFormats.td
llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s
llvm/test/MC/AArch64/SME2/sqdmulh.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index 127203657863..376c27e7d57a 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -272,6 +272,8 @@ defm FSUB_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"fsub", 0b01>;
defm SQDMULH_2ZZ : sme2_sqdmulh_add_vector_vg2_single<"sqdmulh", 0b100000>;
defm SQDMULH_4ZZ : sme2_sqdmulh_add_vector_vg4_single<"sqdmulh", 0b100000>;
+defm SQDMULH_2Z2Z2Z : sme2_sqdmulh_vector_vg2_multi<"sqdmulh">;
+defm SQDMULH_4Z4Z4Z : sme2_sqdmulh_vector_vg4_multi<"sqdmulh">;
defm FMLAL_MZZI : sme2_mla_long_array_index<"fmlal", 0b10, 0b00>;
defm FMLAL_VG2_M2ZZI : sme2_fp_mla_long_array_vg2_index<"fmlal", 0b00>;
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index 96321f505d84..948e15faadd4 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -1474,6 +1474,55 @@ multiclass sme2_sqdmulh_add_vector_vg4_single<string mnemonic, bits<6> op> {
def _D : sme2_sqdmulh_add_vector_vg4_single<0b11, op, ZZZZ_d_mul_r, ZPR4b64, mnemonic>;
}
+
+class sme2_sqdmulh_vector_vg2_multi<bits<2> sz, RegisterOperand vector_ty,
+ string mnemonic>
+ : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, vector_ty:$Zm),
+ mnemonic, "\t$Zdn, $_Zdn, $Zm",
+ "", []>, Sched<[]> {
+ bits<4> Zm;
+ bits<4> Zdn;
+ let Inst{31-24} = 0b11000001;
+ let Inst{23-22} = sz;
+ let Inst{21} = 0b1;
+ let Inst{20-17} = Zm;
+ let Inst{16-5} = 0b010110100000;
+ let Inst{4-1} = Zdn;
+ let Inst{0} = 0b0;
+ let Constraints = "$Zdn = $_Zdn";
+}
+
+multiclass sme2_sqdmulh_vector_vg2_multi<string mnemonic> {
+ def _B : sme2_sqdmulh_vector_vg2_multi<0b00, ZZ_b_mul_r, mnemonic>;
+ def _H : sme2_sqdmulh_vector_vg2_multi<0b01, ZZ_h_mul_r, mnemonic>;
+ def _S : sme2_sqdmulh_vector_vg2_multi<0b10, ZZ_s_mul_r, mnemonic>;
+ def _D : sme2_sqdmulh_vector_vg2_multi<0b11, ZZ_d_mul_r, mnemonic>;
+}
+
+class sme2_sqdmulh_vector_vg4_multi<bits<2> sz, RegisterOperand vector_ty,
+ string mnemonic>
+ : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, vector_ty:$Zm),
+ mnemonic, "\t$Zdn, $_Zdn, $Zm",
+ "", []>, Sched<[]> {
+ bits<3> Zm;
+ bits<3> Zdn;
+ let Inst{31-24} = 0b11000001;
+ let Inst{23-22} = sz;
+ let Inst{21} = 0b1;
+ let Inst{20-18} = Zm;
+ let Inst{17-5} = 0b0010111100000;
+ let Inst{4-2} = Zdn;
+ let Inst{1-0} = 0b00;
+ let Constraints = "$Zdn = $_Zdn";
+}
+
+multiclass sme2_sqdmulh_vector_vg4_multi<string mnemonic> {
+ def _B : sme2_sqdmulh_vector_vg4_multi<0b00, ZZZZ_b_mul_r, mnemonic>;
+ def _H : sme2_sqdmulh_vector_vg4_multi<0b01, ZZZZ_h_mul_r, mnemonic>;
+ def _S : sme2_sqdmulh_vector_vg4_multi<0b10, ZZZZ_s_mul_r, mnemonic>;
+ def _D : sme2_sqdmulh_vector_vg4_multi<0b11, ZZZZ_d_mul_r, mnemonic>;
+}
+
//===----------------------------------------------------------------------===//
// SME2 Multi-vector - Index/Single/Multi Array Vectors FMA sources
@@ -1745,4 +1794,3 @@ multiclass sme2_int_cvt_vg4_single<string mnemonic, bits<3> op> {
def _StoB : sme2_cvt_vg4_single<0b0, op, ZPR8, ZZZZ_s_mul_r, mnemonic>;
def _DtoH : sme2_cvt_vg4_single<0b1, op, ZPR16, ZZZZ_d_mul_r, mnemonic>;
}
-
diff --git a/llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s b/llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s
index 2020d5d550bd..8c101d0933d3 100644
--- a/llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s
@@ -28,6 +28,16 @@ sqdmulh {z28.h-z29.h}, {z1.h-z2.h}, z15.b
// CHECK-NEXT: sqdmulh {z28.h-z29.h}, {z1.h-z2.h}, z15.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+sqdmulh {z1.d-z4.d}, {z1.d-z4.d}, {z8.d-z11.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: sqdmulh {z1.d-z4.d}, {z1.d-z4.d}, {z8.d-z11.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdmulh {z1.d-z2.d}, {z1.d-z2.d}, {z2.d-z3.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: sqdmulh {z1.d-z2.d}, {z1.d-z2.d}, {z2.d-z3.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}
+
// --------------------------------------------------------------------------//
// Invalid single vector register
@@ -77,3 +87,12 @@ sqdmulh {z0.s,z1.s}, {z0.d,z1.d}, z15.s
// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.d,z1.d}, z15.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+sqdmulh {z2.d,z3.d}, {z0.d,z1.d}, {z4.d,z5.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
+// CHECK-NEXT: sqdmulh {z2.d,z3.d}, {z0.d,z1.d}, {z4.d,z5.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdmulh {z0.d-z3.d}, {z4.d-z7.d}, {z0.d-z3.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
+// CHECK-NEXT: sqdmulh {z0.d-z3.d}, {z4.d-z7.d}, {z0.d-z3.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/sqdmulh.s b/llvm/test/MC/AArch64/SME2/sqdmulh.s
index 2c26ba438524..0efb0caac5c2 100644
--- a/llvm/test/MC/AArch64/SME2/sqdmulh.s
+++ b/llvm/test/MC/AArch64/SME2/sqdmulh.s
@@ -37,6 +37,31 @@ sqdmulh {z30.h - z31.h}, {z30.h - z31.h}, z15.h // 11000001-01101111-10100100-0
// CHECK-UNKNOWN: c16fa41e <unknown>
+sqdmulh {z0.h - z1.h}, {z0.h - z1.h}, {z0.h - z1.h} // 11000001-01100000-10110100-00000000
+// CHECK-INST: sqdmulh { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x00,0xb4,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160b400 <unknown>
+
+sqdmulh {z20.h - z21.h}, {z20.h - z21.h}, {z20.h - z21.h} // 11000001-01110100-10110100-00010100
+// CHECK-INST: sqdmulh { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x14,0xb4,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174b414 <unknown>
+
+sqdmulh {z22.h - z23.h}, {z22.h - z23.h}, {z8.h - z9.h} // 11000001-01101000-10110100-00010110
+// CHECK-INST: sqdmulh { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
+// CHECK-ENCODING: [0x16,0xb4,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168b416 <unknown>
+
+sqdmulh {z30.h - z31.h}, {z30.h - z31.h}, {z30.h - z31.h} // 11000001-01111110-10110100-00011110
+// CHECK-INST: sqdmulh { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x1e,0xb4,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17eb41e <unknown>
+
+
sqdmulh {z0.s - z1.s}, {z0.s - z1.s}, z0.s // 11000001-10100000-10100100-00000000
// CHECK-INST: sqdmulh { z0.s, z1.s }, { z0.s, z1.s }, z0.s
// CHECK-ENCODING: [0x00,0xa4,0xa0,0xc1]
@@ -62,6 +87,31 @@ sqdmulh {z30.s - z31.s}, {z30.s - z31.s}, z15.s // 11000001-10101111-10100100-0
// CHECK-UNKNOWN: c1afa41e <unknown>
+sqdmulh {z0.s - z1.s}, {z0.s - z1.s}, {z0.s - z1.s} // 11000001-10100000-10110100-00000000
+// CHECK-INST: sqdmulh { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0xb4,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0b400 <unknown>
+
+sqdmulh {z20.s - z21.s}, {z20.s - z21.s}, {z20.s - z21.s} // 11000001-10110100-10110100-00010100
+// CHECK-INST: sqdmulh { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x14,0xb4,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4b414 <unknown>
+
+sqdmulh {z22.s - z23.s}, {z22.s - z23.s}, {z8.s - z9.s} // 11000001-10101000-10110100-00010110
+// CHECK-INST: sqdmulh { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x16,0xb4,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8b416 <unknown>
+
+sqdmulh {z30.s - z31.s}, {z30.s - z31.s}, {z30.s - z31.s} // 11000001-10111110-10110100-00011110
+// CHECK-INST: sqdmulh { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x1e,0xb4,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1beb41e <unknown>
+
+
sqdmulh {z0.d - z1.d}, {z0.d - z1.d}, z0.d // 11000001-11100000-10100100-00000000
// CHECK-INST: sqdmulh { z0.d, z1.d }, { z0.d, z1.d }, z0.d
// CHECK-ENCODING: [0x00,0xa4,0xe0,0xc1]
@@ -87,6 +137,31 @@ sqdmulh {z30.d - z31.d}, {z30.d - z31.d}, z15.d // 11000001-11101111-10100100-0
// CHECK-UNKNOWN: c1efa41e <unknown>
+sqdmulh {z0.d - z1.d}, {z0.d - z1.d}, {z0.d - z1.d} // 11000001-11100000-10110100-00000000
+// CHECK-INST: sqdmulh { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x00,0xb4,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0b400 <unknown>
+
+sqdmulh {z20.d - z21.d}, {z20.d - z21.d}, {z20.d - z21.d} // 11000001-11110100-10110100-00010100
+// CHECK-INST: sqdmulh { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x14,0xb4,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4b414 <unknown>
+
+sqdmulh {z22.d - z23.d}, {z22.d - z23.d}, {z8.d - z9.d} // 11000001-11101000-10110100-00010110
+// CHECK-INST: sqdmulh { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x16,0xb4,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8b416 <unknown>
+
+sqdmulh {z30.d - z31.d}, {z30.d - z31.d}, {z30.d - z31.d} // 11000001-11111110-10110100-00011110
+// CHECK-INST: sqdmulh { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x1e,0xb4,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1feb41e <unknown>
+
+
sqdmulh {z0.b - z1.b}, {z0.b - z1.b}, z0.b // 11000001-00100000-10100100-00000000
// CHECK-INST: sqdmulh { z0.b, z1.b }, { z0.b, z1.b }, z0.b
// CHECK-ENCODING: [0x00,0xa4,0x20,0xc1]
@@ -112,6 +187,31 @@ sqdmulh {z30.b - z31.b}, {z30.b - z31.b}, z15.b // 11000001-00101111-10100100-0
// CHECK-UNKNOWN: c12fa41e <unknown>
+sqdmulh {z0.b - z1.b}, {z0.b - z1.b}, {z0.b - z1.b} // 11000001-00100000-10110100-00000000
+// CHECK-INST: sqdmulh { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x00,0xb4,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120b400 <unknown>
+
+sqdmulh {z20.b - z21.b}, {z20.b - z21.b}, {z20.b - z21.b} // 11000001-00110100-10110100-00010100
+// CHECK-INST: sqdmulh { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }
+// CHECK-ENCODING: [0x14,0xb4,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134b414 <unknown>
+
+sqdmulh {z22.b - z23.b}, {z22.b - z23.b}, {z8.b - z9.b} // 11000001-00101000-10110100-00010110
+// CHECK-INST: sqdmulh { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }
+// CHECK-ENCODING: [0x16,0xb4,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128b416 <unknown>
+
+sqdmulh {z30.b - z31.b}, {z30.b - z31.b}, {z30.b - z31.b} // 11000001-00111110-10110100-00011110
+// CHECK-INST: sqdmulh { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }
+// CHECK-ENCODING: [0x1e,0xb4,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13eb41e <unknown>
+
+
sqdmulh {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101100-00000000
// CHECK-INST: sqdmulh { z0.h - z3.h }, { z0.h - z3.h }, z0.h
// CHECK-ENCODING: [0x00,0xac,0x60,0xc1]
@@ -137,6 +237,31 @@ sqdmulh {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101100-0
// CHECK-UNKNOWN: c16fac1c <unknown>
+sqdmulh {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111100-00000000
+// CHECK-INST: sqdmulh { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x00,0xbc,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160bc00 <unknown>
+
+sqdmulh {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111100-00010100
+// CHECK-INST: sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x14,0xbc,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c174bc14 <unknown>
+
+sqdmulh {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111100-00010100
+// CHECK-INST: sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x14,0xbc,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168bc14 <unknown>
+
+sqdmulh {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111100-00011100
+// CHECK-INST: sqdmulh { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x1c,0xbc,0x7c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17cbc1c <unknown>
+
+
sqdmulh {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101100-00000000
// CHECK-INST: sqdmulh { z0.s - z3.s }, { z0.s - z3.s }, z0.s
// CHECK-ENCODING: [0x00,0xac,0xa0,0xc1]
@@ -162,6 +287,31 @@ sqdmulh {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101100-0
// CHECK-UNKNOWN: c1afac1c <unknown>
+sqdmulh {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111100-00000000
+// CHECK-INST: sqdmulh { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0xbc,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0bc00 <unknown>
+
+sqdmulh {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111100-00010100
+// CHECK-INST: sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x14,0xbc,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4bc14 <unknown>
+
+sqdmulh {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111100-00010100
+// CHECK-INST: sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x14,0xbc,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8bc14 <unknown>
+
+sqdmulh {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111100-00011100
+// CHECK-INST: sqdmulh { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x1c,0xbc,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bcbc1c <unknown>
+
+
sqdmulh {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101100-00000000
// CHECK-INST: sqdmulh { z0.d - z3.d }, { z0.d - z3.d }, z0.d
// CHECK-ENCODING: [0x00,0xac,0xe0,0xc1]
@@ -187,6 +337,31 @@ sqdmulh {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101100-0
// CHECK-UNKNOWN: c1efac1c <unknown>
+sqdmulh {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111100-00000000
+// CHECK-INST: sqdmulh { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x00,0xbc,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0bc00 <unknown>
+
+sqdmulh {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111100-00010100
+// CHECK-INST: sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x14,0xbc,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4bc14 <unknown>
+
+sqdmulh {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111100-00010100
+// CHECK-INST: sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x14,0xbc,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8bc14 <unknown>
+
+sqdmulh {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111100-00011100
+// CHECK-INST: sqdmulh { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x1c,0xbc,0xfc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fcbc1c <unknown>
+
+
sqdmulh {z0.b - z3.b}, {z0.b - z3.b}, z0.b // 11000001-00100000-10101100-00000000
// CHECK-INST: sqdmulh { z0.b - z3.b }, { z0.b - z3.b }, z0.b
// CHECK-ENCODING: [0x00,0xac,0x20,0xc1]
@@ -210,3 +385,29 @@ sqdmulh {z28.b - z31.b}, {z28.b - z31.b}, z15.b // 11000001-00101111-10101100-0
// CHECK-ENCODING: [0x1c,0xac,0x2f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12fac1c <unknown>
+
+
+sqdmulh {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b} // 11000001-00100000-10111100-00000000
+// CHECK-INST: sqdmulh { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x00,0xbc,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120bc00 <unknown>
+
+sqdmulh {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b} // 11000001-00110100-10111100-00010100
+// CHECK-INST: sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }
+// CHECK-ENCODING: [0x14,0xbc,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c134bc14 <unknown>
+
+sqdmulh {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b} // 11000001-00101000-10111100-00010100
+// CHECK-INST: sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x14,0xbc,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128bc14 <unknown>
+
+sqdmulh {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b} // 11000001-00111100-10111100-00011100
+// CHECK-INST: sqdmulh { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x1c,0xbc,0x3c,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13cbc1c <unknown>
+
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