[llvm] 3bee2fb - [AArch64] SME2 Multiple vectors int/float binary accumulator and two/four ZA single-vector
Caroline Concatto via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 21 06:47:07 PDT 2022
Author: Caroline Concatto
Date: 2022-10-21T14:46:35+01:00
New Revision: 3bee2fb26222b71ba30234586dc0e6c197358091
URL: https://github.com/llvm/llvm-project/commit/3bee2fb26222b71ba30234586dc0e6c197358091
DIFF: https://github.com/llvm/llvm-project/commit/3bee2fb26222b71ba30234586dc0e6c197358091.diff
LOG: [AArch64] SME2 Multiple vectors int/float binary accumulator and two/four ZA single-vector
This patch adds the assembly/disassembly for the following instructions:
INT :
ADD (array accumulators): Add multi-vector to ZA array vector accumulators.
SUB (array accumulators): Subtract multi-vector from ZA array vector accumulators.
FP:
FADD : Floating-point add multi-vector to ZA array vector accumulators.
FSUB : Floating-point subtract multi-vector from ZA array vector accumulators.
For Two and Four ZA single-vectors
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Depends on: D135563
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D135567
Added:
llvm/test/MC/AArch64/SME2/fadd-diagnostics.s
llvm/test/MC/AArch64/SME2/fadd.s
llvm/test/MC/AArch64/SME2/fsub-diagnostics.s
llvm/test/MC/AArch64/SME2/fsub.s
Modified:
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
llvm/lib/Target/AArch64/SMEInstrFormats.td
llvm/test/MC/AArch64/SME2/add-diagnostics.s
llvm/test/MC/AArch64/SME2/add.s
llvm/test/MC/AArch64/SME2/sub-diagnostics.s
llvm/test/MC/AArch64/SME2/sub.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index e85e90462397..3dec59f338a5 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -270,6 +270,18 @@ defm FMLS_VG4_M4Z4Z_S : sme2_mla_add_sub_array_vg4_multi_S<"fmls", 0b01>;
defm ADD_VG2_2ZZ : sme2_sqdmulh_add_vector_vg2_single<"add", 0b011000>;
defm ADD_VG4_4ZZ : sme2_sqdmulh_add_vector_vg4_single<"add", 0b011000>;
+defm ADDA_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"add", 0b10>;
+defm ADDA_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"add", 0b10>;
+
+defm SUBA_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"sub", 0b11>;
+defm SUBA_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"sub", 0b11>;
+
+defm FADD_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"fadd", 0b00>;
+defm FADD_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"fadd", 0b00>;
+
+defm FSUB_VG2_M2Z2Z_S : sme2_multivec_accum_add_sub_vg2_S<"fsub", 0b01>;
+defm FSUB_VG4_M4Z4Z_S : sme2_multivec_accum_add_sub_vg4_S<"fsub", 0b01>;
+
defm SQDMULH_2ZZ : sme2_sqdmulh_add_vector_vg2_single<"sqdmulh", 0b100000>;
defm SQDMULH_4ZZ : sme2_sqdmulh_add_vector_vg4_single<"sqdmulh", 0b100000>;
@@ -373,6 +385,12 @@ defm SUB_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"sub", 0b11>;
defm SUB_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"sub", 0b11>;
defm SUB_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"sub", 0b11>;
defm SUB_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"sub", 0b11>;
+
+defm ADDA_VG2_M2Z2Z_D : sme2_multivec_accum_add_sub_vg2_D<"add", 0b10>;
+defm ADDA_VG4_M4Z4Z_D : sme2_multivec_accum_add_sub_vg4_D<"add", 0b10>;
+
+defm SUBA_VG2_M2Z2Z_D : sme2_multivec_accum_add_sub_vg2_D<"sub", 0b11>;
+defm SUBA_VG4_M4Z4Z_D : sme2_multivec_accum_add_sub_vg4_D<"sub", 0b11>;
}
let Predicates = [HasSME2, HasSMEF64F64] in {
@@ -385,4 +403,10 @@ defm FMLS_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"fmls", 0b01>;
defm FMLS_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"fmls", 0b01>;
defm FMLS_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"fmls", 0b01>;
defm FMLS_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"fmls", 0b01>;
+
+defm FADD_VG2_M2Z2Z_D : sme2_multivec_accum_add_sub_vg2_D<"fadd", 0b00>;
+defm FADD_VG4_M4Z4Z_D : sme2_multivec_accum_add_sub_vg4_D<"fadd", 0b00>;
+
+defm FSUB_VG2_M2Z2Z_D : sme2_multivec_accum_add_sub_vg2_D<"fsub", 0b01>;
+defm FSUB_VG4_M4Z4Z_D : sme2_multivec_accum_add_sub_vg4_D<"fsub", 0b01>;
}
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index a719a7ae63bb..96321f505d84 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -1338,6 +1338,86 @@ multiclass sme2_mla_add_sub_array_vg4_multi_D<string mnemonic, bits<2> op>{
(!cast<Instruction>(NAME) MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZZZ_d_mul_r:$Zn, ZZZZ_d_mul_r:$Zm), 0>;
}
+//===----------------------------------------------------------------------===//
+// SME2 multiple vectors binary two or four registers
+
+class sme2_multivec_accum_add_sub<string mnemonic, bit sz, bit is_int,
+ bit s, MatrixOperand matrix_ty,
+ RegisterOperand vector_ty,
+ string vg_acronym>
+ : I<(outs matrix_ty:$ZAdn),
+ (ins matrix_ty:$_ZAdn, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, vector_ty:$Zm),
+ mnemonic, "\t$ZAdn[$Rv, $imm3, " # vg_acronym # "], $Zm",
+ "", []>, Sched<[]> {
+ bits<2> Rv;
+ bits<3> imm3;
+ let Inst{31-23} = 0b110000011;
+ let Inst{22} = sz;
+ let Inst{21-17} = 0b10000;
+ let Inst{15} = 0b0;
+ let Inst{14-13} = Rv;
+ let Inst{12-10} = 0b111;
+ let Inst{5} = 0b0;
+ let Inst{4} = is_int;
+ let Inst{3} = s;
+ let Inst{2-0} = imm3;
+
+ let Constraints = "$ZAdn = $_ZAdn";
+}
+
+class sme2_multivec_accum_add_sub_vg2<string mnemonic, bit sz, bit is_int,
+ bit s, MatrixOperand matrix_ty,
+ RegisterOperand vector_ty>
+ : sme2_multivec_accum_add_sub<mnemonic, sz, is_int, s,
+ matrix_ty, vector_ty , "vgx2"> {
+ bits<4> Zm;
+ let Inst{16} = 0b0;
+ let Inst{9-6} = Zm;
+}
+
+
+multiclass sme2_multivec_accum_add_sub_vg2_S<string mnemonic, bits<2> op> {
+ def NAME : sme2_multivec_accum_add_sub_vg2<mnemonic, 0b0, op{1}, op{0},
+ MatrixOp32, ZZ_s_mul_r>;
+
+ def : InstAlias<mnemonic # "\t$ZAdn[$Rv, $imm3], $Zm",
+ (!cast<Instruction>(NAME) MatrixOp32:$ZAdn, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZ_s_mul_r:$Zm), 0>;
+}
+
+multiclass sme2_multivec_accum_add_sub_vg2_D<string mnemonic, bits<2> op> {
+ def NAME : sme2_multivec_accum_add_sub_vg2<mnemonic, 0b1, op{1}, op{0},
+ MatrixOp64, ZZ_d_mul_r>;
+ def : InstAlias<mnemonic # "\t$ZAdn[$Rv, $imm3], $Zm",
+ (!cast<Instruction>(NAME) MatrixOp64:$ZAdn, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZ_d_mul_r:$Zm), 0>;
+
+}
+
+class sme2_multivec_accum_add_sub_vg4<string mnemonic, bit sz, bit is_int,
+ bit s, MatrixOperand matrix_ty,
+ RegisterOperand vector_ty>
+ : sme2_multivec_accum_add_sub<mnemonic, sz, is_int, s,
+ matrix_ty, vector_ty , "vgx4"> {
+ bits<3> Zm;
+ let Inst{16} = 0b1;
+ let Inst{9-7} = Zm;
+ let Inst{6} = 0b0;
+}
+
+multiclass sme2_multivec_accum_add_sub_vg4_S<string mnemonic, bits<2> op> {
+ def NAME : sme2_multivec_accum_add_sub_vg4<mnemonic, 0b0, op{1}, op{0},
+ MatrixOp32, ZZZZ_s_mul_r>;
+
+ def : InstAlias<mnemonic # "\t$ZAdn[$Rv, $imm3], $Zm",
+ (!cast<Instruction>(NAME) MatrixOp32:$ZAdn, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZZZ_s_mul_r:$Zm), 0>;
+}
+
+multiclass sme2_multivec_accum_add_sub_vg4_D<string mnemonic, bits<2> op> {
+ def NAME : sme2_multivec_accum_add_sub_vg4<mnemonic, 0b1, op{1}, op{0},
+ MatrixOp64, ZZZZ_d_mul_r>;
+ def : InstAlias<mnemonic # "\t$ZAdn[$Rv, $imm3], $Zm",
+ (!cast<Instruction>(NAME) MatrixOp64:$ZAdn, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZZZ_d_mul_r:$Zm), 0>;
+}
+
//===----------------------------------------------------------------------===//
// SME2 Multi-vector - Multiple and Single SVE Destructive
// Two and Four registers
diff --git a/llvm/test/MC/AArch64/SME2/add-diagnostics.s b/llvm/test/MC/AArch64/SME2/add-diagnostics.s
index 9feb2b497bb6..bea98a0afa97 100644
--- a/llvm/test/MC/AArch64/SME2/add-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2/add-diagnostics.s
@@ -23,6 +23,17 @@ add za.s[w8, -1], {z0.s - z3.s}, {z4.s - z7.s}
// CHECK-NEXT: add za.s[w8, -1], {z0.s - z3.s}, {z4.s - z7.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+add za.d[w8, 8, vgx4], {z0.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: za.d[w8, 8, vgx4], {z0.s-z3.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+add za.d[w8, -1, vgx4], {z0.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: za.d[w8, -1, vgx4], {z0.s-z3.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
// --------------------------------------------------------------------------//
// Invalid vector select register
@@ -49,6 +60,11 @@ add za.h[w8, #0], {z0.h-z3.h}, z4.h
// CHECK-NEXT: add za.h[w8, #0], {z0.h-z3.h}, z4.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+add za.h[w8, 0, vgx2], {z0.s, z1.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .d
+// CHECK-NEXT: za.h[w8, 0, vgx2], {z0.s, z1.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector grouping
diff --git a/llvm/test/MC/AArch64/SME2/add.s b/llvm/test/MC/AArch64/SME2/add.s
index 89aa78793d39..82f11c92671c 100644
--- a/llvm/test/MC/AArch64/SME2/add.s
+++ b/llvm/test/MC/AArch64/SME2/add.s
@@ -37,6 +37,142 @@ add {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100011-000
// CHECK-UNKNOWN: c16fa31e <unknown>
+add za.s[w8, 0, vgx2], {z0.s, z1.s} // 11000001-10100000-00011100-00010000
+// CHECK-INST: add za.s[w8, 0, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x10,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c10 <unknown>
+
+add za.s[w8, 0], {z0.s, z1.s} // 11000001-10100000-00011100-00010000
+// CHECK-INST: add za.s[w8, 0, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x10,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c10 <unknown>
+
+add za.s[w10, 5, vgx2], {z10.s, z11.s} // 11000001-10100000-01011101-01010101
+// CHECK-INST: add za.s[w10, 5, vgx2], { z10.s, z11.s }
+// CHECK-ENCODING: [0x55,0x5d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05d55 <unknown>
+
+add za.s[w10, 5], {z10.s, z11.s} // 11000001-10100000-01011101-01010101
+// CHECK-INST: add za.s[w10, 5, vgx2], { z10.s, z11.s }
+// CHECK-ENCODING: [0x55,0x5d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05d55 <unknown>
+
+add za.s[w11, 7, vgx2], {z12.s, z13.s} // 11000001-10100000-01111101-10010111
+// CHECK-INST: add za.s[w11, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x97,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d97 <unknown>
+
+add za.s[w11, 7], {z12.s, z13.s} // 11000001-10100000-01111101-10010111
+// CHECK-INST: add za.s[w11, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x97,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d97 <unknown>
+
+add za.s[w11, 7, vgx2], {z30.s, z31.s} // 11000001-10100000-01111111-11010111
+// CHECK-INST: add za.s[w11, 7, vgx2], { z30.s, z31.s }
+// CHECK-ENCODING: [0xd7,0x7f,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07fd7 <unknown>
+
+add za.s[w11, 7], {z30.s, z31.s} // 11000001-10100000-01111111-11010111
+// CHECK-INST: add za.s[w11, 7, vgx2], { z30.s, z31.s }
+// CHECK-ENCODING: [0xd7,0x7f,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07fd7 <unknown>
+
+add za.s[w8, 5, vgx2], {z16.s, z17.s} // 11000001-10100000-00011110-00010101
+// CHECK-INST: add za.s[w8, 5, vgx2], { z16.s, z17.s }
+// CHECK-ENCODING: [0x15,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01e15 <unknown>
+
+add za.s[w8, 5], {z16.s, z17.s} // 11000001-10100000-00011110-00010101
+// CHECK-INST: add za.s[w8, 5, vgx2], { z16.s, z17.s }
+// CHECK-ENCODING: [0x15,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01e15 <unknown>
+
+add za.s[w8, 1, vgx2], {z0.s, z1.s} // 11000001-10100000-00011100-00010001
+// CHECK-INST: add za.s[w8, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x11,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c11 <unknown>
+
+add za.s[w8, 1], {z0.s, z1.s} // 11000001-10100000-00011100-00010001
+// CHECK-INST: add za.s[w8, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x11,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c11 <unknown>
+
+add za.s[w10, 0, vgx2], {z18.s, z19.s} // 11000001-10100000-01011110-01010000
+// CHECK-INST: add za.s[w10, 0, vgx2], { z18.s, z19.s }
+// CHECK-ENCODING: [0x50,0x5e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05e50 <unknown>
+
+add za.s[w10, 0], {z18.s, z19.s} // 11000001-10100000-01011110-01010000
+// CHECK-INST: add za.s[w10, 0, vgx2], { z18.s, z19.s }
+// CHECK-ENCODING: [0x50,0x5e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+
+add za.s[w8, 0], {z12.s, z13.s} // 11000001-10100000-00011101-10010000
+// CHECK-INST: add za.s[w8, 0, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x90,0x1d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01d90 <unknown>
+
+add za.s[w10, 1, vgx2], {z0.s, z1.s} // 11000001-10100000-01011100-00010001
+// CHECK-INST: add za.s[w10, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x11,0x5c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05c11 <unknown>
+
+add za.s[w10, 1], {z0.s, z1.s} // 11000001-10100000-01011100-00010001
+// CHECK-INST: add za.s[w10, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x11,0x5c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05c11 <unknown>
+
+add za.s[w8, 5, vgx2], {z22.s, z23.s} // 11000001-10100000-00011110-11010101
+// CHECK-INST: add za.s[w8, 5, vgx2], { z22.s, z23.s }
+// CHECK-ENCODING: [0xd5,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01ed5 <unknown>
+
+add za.s[w8, 5], {z22.s, z23.s} // 11000001-10100000-00011110-11010101
+// CHECK-INST: add za.s[w8, 5, vgx2], { z22.s, z23.s }
+// CHECK-ENCODING: [0xd5,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01ed5 <unknown>
+
+add za.s[w11, 2, vgx2], {z8.s, z9.s} // 11000001-10100000-01111101-00010010
+// CHECK-INST: add za.s[w11, 2, vgx2], { z8.s, z9.s }
+// CHECK-ENCODING: [0x12,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d12 <unknown>
+
+add za.s[w11, 2], {z8.s, z9.s} // 11000001-10100000-01111101-00010010
+// CHECK-INST: add za.s[w11, 2, vgx2], { z8.s, z9.s }
+// CHECK-ENCODING: [0x12,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d12 <unknown>
+
+add za.s[w9, 7, vgx2], {z12.s, z13.s} // 11000001-10100000-00111101-10010111
+// CHECK-INST: add za.s[w9, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x97,0x3d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a03d97 <unknown>
+
+add za.s[w9, 7], {z12.s, z13.s} // 11000001-10100000-00111101-10010111
+// CHECK-INST: add za.s[w9, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x97,0x3d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a03d97 <unknown>
add za.s[w8, 0, vgx2], {z0.s, z1.s}, z0.s // 11000001, 00100000, 00011000, 00010000
// CHECK-INST: add za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s
// CHECK-ENCODING: [0x10,0x18,0x20,0xc1]
@@ -352,6 +488,151 @@ add za.s[w9, 7], {z12.s - z13.s}, {z10.s - z11.s} // 11000001-10101010-0011
// CHECK-UNKNOWN: c1aa3997 <unknown>
+add za.d[w8, 0, vgx2], {z0.d, z1.d} // 11000001-11100000-00011100-00010000
+// CHECK-INST: add za.d[w8, 0, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x10,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01c10 <unknown>
+
+add za.d[w8, 0], {z0.d, z1.d} // 11000001-11100000-00011100-00010000
+// CHECK-INST: add za.d[w8, 0, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x10,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01c10 <unknown>
+
+add za.d[w10, 5, vgx2], {z10.d, z11.d} // 11000001-11100000-01011101-01010101
+// CHECK-INST: add za.d[w10, 5, vgx2], { z10.d, z11.d }
+// CHECK-ENCODING: [0x55,0x5d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e05d55 <unknown>
+
+add za.d[w10, 5], {z10.d, z11.d} // 11000001-11100000-01011101-01010101
+// CHECK-INST: add za.d[w10, 5, vgx2], { z10.d, z11.d }
+// CHECK-ENCODING: [0x55,0x5d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e05d55 <unknown>
+
+add za.d[w11, 7, vgx2], {z12.d, z13.d} // 11000001-11100000-01111101-10010111
+// CHECK-INST: add za.d[w11, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x97,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07d97 <unknown>
+
+add za.d[w11, 7], {z12.d, z13.d} // 11000001-11100000-01111101-10010111
+// CHECK-INST: add za.d[w11, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x97,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07d97 <unknown>
+
+add za.d[w11, 7, vgx2], {z30.d, z31.d} // 11000001-11100000-01111111-11010111
+// CHECK-INST: add za.d[w11, 7, vgx2], { z30.d, z31.d }
+// CHECK-ENCODING: [0xd7,0x7f,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07fd7 <unknown>
+
+add za.d[w11, 7], {z30.d, z31.d} // 11000001-11100000-01111111-11010111
+// CHECK-INST: add za.d[w11, 7, vgx2], { z30.d, z31.d }
+// CHECK-ENCODING: [0xd7,0x7f,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07fd7 <unknown>
+
+add za.d[w8, 5, vgx2], {z16.d, z17.d} // 11000001-11100000-00011110-00010101
+// CHECK-INST: add za.d[w8, 5, vgx2], { z16.d, z17.d }
+// CHECK-ENCODING: [0x15,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01e15 <unknown>
+
+add za.d[w8, 5], {z16.d, z17.d} // 11000001-11100000-00011110-00010101
+// CHECK-INST: add za.d[w8, 5, vgx2], { z16.d, z17.d }
+// CHECK-ENCODING: [0x15,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01e15 <unknown>
+
+add za.d[w8, 1, vgx2], {z0.d, z1.d} // 11000001-11100000-00011100-00010001
+// CHECK-INST: add za.d[w8, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x11,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01c11 <unknown>
+
+add za.d[w8, 1], {z0.d, z1.d} // 11000001-11100000-00011100-00010001
+// CHECK-INST: add za.d[w8, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x11,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01c11 <unknown>
+
+add za.d[w10, 0, vgx2], {z18.d, z19.d} // 11000001-11100000-01011110-01010000
+// CHECK-INST: add za.d[w10, 0, vgx2], { z18.d, z19.d }
+// CHECK-ENCODING: [0x50,0x5e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e05e50 <unknown>
+
+add za.d[w10, 0], {z18.d, z19.d} // 11000001-11100000-01011110-01010000
+// CHECK-INST: add za.d[w10, 0, vgx2], { z18.d, z19.d }
+// CHECK-ENCODING: [0x50,0x5e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e05e50 <unknown>
+
+add za.d[w8, 0, vgx2], {z12.d, z13.d} // 11000001-11100000-00011101-10010000
+// CHECK-INST: add za.d[w8, 0, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x90,0x1d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01d90 <unknown>
+
+add za.d[w8, 0], {z12.d, z13.d} // 11000001-11100000-00011101-10010000
+// CHECK-INST: add za.d[w8, 0, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x90,0x1d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01d90 <unknown>
+
+add za.d[w10, 1, vgx2], {z0.d, z1.d} // 11000001-11100000-01011100-00010001
+// CHECK-INST: add za.d[w10, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x11,0x5c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e05c11 <unknown>
+
+add za.d[w10, 1], {z0.d, z1.d} // 11000001-11100000-01011100-00010001
+// CHECK-INST: add za.d[w10, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x11,0x5c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e05c11 <unknown>
+
+add za.d[w8, 5, vgx2], {z22.d, z23.d} // 11000001-11100000-00011110-11010101
+// CHECK-INST: add za.d[w8, 5, vgx2], { z22.d, z23.d }
+// CHECK-ENCODING: [0xd5,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01ed5 <unknown>
+
+add za.d[w8, 5], {z22.d, z23.d} // 11000001-11100000-00011110-11010101
+// CHECK-INST: add za.d[w8, 5, vgx2], { z22.d, z23.d }
+// CHECK-ENCODING: [0xd5,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01ed5 <unknown>
+
+add za.d[w11, 2, vgx2], {z8.d, z9.d} // 11000001-11100000-01111101-00010010
+// CHECK-INST: add za.d[w11, 2, vgx2], { z8.d, z9.d }
+// CHECK-ENCODING: [0x12,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07d12 <unknown>
+
+add za.d[w11, 2], {z8.d, z9.d} // 11000001-11100000-01111101-00010010
+// CHECK-INST: add za.d[w11, 2, vgx2], { z8.d, z9.d }
+// CHECK-ENCODING: [0x12,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07d12 <unknown>
+
+add za.d[w9, 7, vgx2], {z12.d, z13.d} // 11000001-11100000-00111101-10010111
+// CHECK-INST: add za.d[w9, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x97,0x3d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e03d97 <unknown>
+
+add za.d[w9, 7], {z12.d, z13.d} // 11000001-11100000-00111101-10010111
+// CHECK-INST: add za.d[w9, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x97,0x3d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e03d97 <unknown>
+
+
add za.d[w8, 0, vgx2], {z0.d, z1.d}, z0.d // 11000001, 01100000, 00011000, 00010000
// CHECK-INST: add za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d
// CHECK-ENCODING: [0x10,0x18,0x60,0xc1]
@@ -718,7 +999,152 @@ add {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101011-0
// CHECK-UNKNOWN: c16fab1c <unknown>
-add za.s[w8, 0, vgx4], {z0.s-z3.s}, z0.s // 11000001-00110000-00011000-00010000
+add za.s[w8, 0, vgx4], {z0.s - z3.s} // 11000001-10100001-00011100-00010000
+// CHECK-INST: add za.s[w8, 0, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x10,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c10 <unknown>
+
+add za.s[w8, 0], {z0.s - z3.s} // 11000001-10100001-00011100-00010000
+// CHECK-INST: add za.s[w8, 0, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x10,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c10 <unknown>
+
+add za.s[w10, 5, vgx4], {z8.s - z11.s} // 11000001-10100001-01011101-00010101
+// CHECK-INST: add za.s[w10, 5, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x15,0x5d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15d15 <unknown>
+
+add za.s[w10, 5], {z8.s - z11.s} // 11000001-10100001-01011101-00010101
+// CHECK-INST: add za.s[w10, 5, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x15,0x5d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15d15 <unknown>
+
+add za.s[w11, 7, vgx4], {z12.s - z15.s} // 11000001-10100001-01111101-10010111
+// CHECK-INST: add za.s[w11, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x97,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d97 <unknown>
+
+add za.s[w11, 7], {z12.s - z15.s} // 11000001-10100001-01111101-10010111
+// CHECK-INST: add za.s[w11, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x97,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d97 <unknown>
+
+add za.s[w11, 7, vgx4], {z28.s - z31.s} // 11000001-10100001-01111111-10010111
+// CHECK-INST: add za.s[w11, 7, vgx4], { z28.s - z31.s }
+// CHECK-ENCODING: [0x97,0x7f,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17f97 <unknown>
+
+add za.s[w11, 7], {z28.s - z31.s} // 11000001-10100001-01111111-10010111
+// CHECK-INST: add za.s[w11, 7, vgx4], { z28.s - z31.s }
+// CHECK-ENCODING: [0x97,0x7f,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17f97 <unknown>
+
+add za.s[w8, 5, vgx4], {z16.s - z19.s} // 11000001-10100001-00011110-00010101
+// CHECK-INST: add za.s[w8, 5, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x15,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e15 <unknown>
+
+add za.s[w8, 5], {z16.s - z19.s} // 11000001-10100001-00011110-00010101
+// CHECK-INST: add za.s[w8, 5, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x15,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e15 <unknown>
+
+add za.s[w8, 1, vgx4], {z0.s - z3.s} // 11000001-10100001-00011100-00010001
+// CHECK-INST: add za.s[w8, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x11,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c11 <unknown>
+
+add za.s[w8, 1], {z0.s - z3.s} // 11000001-10100001-00011100-00010001
+// CHECK-INST: add za.s[w8, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x11,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c11 <unknown>
+
+add za.s[w10, 0, vgx4], {z16.s - z19.s} // 11000001-10100001-01011110-00010000
+// CHECK-INST: add za.s[w10, 0, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x10,0x5e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15e10 <unknown>
+
+add za.s[w10, 0], {z16.s - z19.s} // 11000001-10100001-01011110-00010000
+// CHECK-INST: add za.s[w10, 0, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x10,0x5e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15e10 <unknown>
+
+add za.s[w8, 0, vgx4], {z12.s - z15.s} // 11000001-10100001-00011101-10010000
+// CHECK-INST: add za.s[w8, 0, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x90,0x1d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11d90 <unknown>
+
+add za.s[w8, 0], {z12.s - z15.s} // 11000001-10100001-00011101-10010000
+// CHECK-INST: add za.s[w8, 0, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x90,0x1d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11d90 <unknown>
+
+add za.s[w10, 1, vgx4], {z0.s - z3.s} // 11000001-10100001-01011100-00010001
+// CHECK-INST: add za.s[w10, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x11,0x5c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15c11 <unknown>
+
+add za.s[w10, 1], {z0.s - z3.s} // 11000001-10100001-01011100-00010001
+// CHECK-INST: add za.s[w10, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x11,0x5c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15c11 <unknown>
+
+add za.s[w8, 5, vgx4], {z20.s - z23.s} // 11000001-10100001-00011110-10010101
+// CHECK-INST: add za.s[w8, 5, vgx4], { z20.s - z23.s }
+// CHECK-ENCODING: [0x95,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e95 <unknown>
+
+add za.s[w8, 5], {z20.s - z23.s} // 11000001-10100001-00011110-10010101
+// CHECK-INST: add za.s[w8, 5, vgx4], { z20.s - z23.s }
+// CHECK-ENCODING: [0x95,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e95 <unknown>
+
+add za.s[w11, 2, vgx4], {z8.s - z11.s} // 11000001-10100001-01111101-00010010
+// CHECK-INST: add za.s[w11, 2, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x12,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d12 <unknown>
+
+add za.s[w11, 2], {z8.s - z11.s} // 11000001-10100001-01111101-00010010
+// CHECK-INST: add za.s[w11, 2, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x12,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d12 <unknown>
+
+add za.s[w9, 7, vgx4], {z12.s - z15.s} // 11000001-10100001-00111101-10010111
+// CHECK-INST: add za.s[w9, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x97,0x3d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a13d97 <unknown>
+
+add za.s[w9, 7], {z12.s - z15.s} // 11000001-10100001-00111101-10010111
+// CHECK-INST: add za.s[w9, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x97,0x3d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a13d97 <unknown>
+
+
+add za.s[w8, 0, vgx4], {z0.s - z3.s}, z0.s // 11000001-00110000-00011000-00010000
// CHECK-INST: add za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
// CHECK-ENCODING: [0x10,0x18,0x30,0xc1]
// CHECK-ERROR: instruction requires: sme2
@@ -1033,6 +1459,151 @@ add za.s[w9, 7], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-00111
// CHECK-UNKNOWN: c1a93997 <unknown>
+add za.d[w8, 0, vgx4], {z0.d - z3.d} // 11000001-11100001-00011100-00010000
+// CHECK-INST: add za.d[w8, 0, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x10,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11c10 <unknown>
+
+add za.d[w8, 0], {z0.d - z3.d} // 11000001-11100001-00011100-00010000
+// CHECK-INST: add za.d[w8, 0, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x10,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11c10 <unknown>
+
+add za.d[w10, 5, vgx4], {z8.d - z11.d} // 11000001-11100001-01011101-00010101
+// CHECK-INST: add za.d[w10, 5, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x15,0x5d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e15d15 <unknown>
+
+add za.d[w10, 5], {z8.d - z11.d} // 11000001-11100001-01011101-00010101
+// CHECK-INST: add za.d[w10, 5, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x15,0x5d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e15d15 <unknown>
+
+add za.d[w11, 7, vgx4], {z12.d - z15.d} // 11000001-11100001-01111101-10010111
+// CHECK-INST: add za.d[w11, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x97,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17d97 <unknown>
+
+add za.d[w11, 7], {z12.d - z15.d} // 11000001-11100001-01111101-10010111
+// CHECK-INST: add za.d[w11, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x97,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17d97 <unknown>
+
+add za.d[w11, 7, vgx4], {z28.d - z31.d} // 11000001-11100001-01111111-10010111
+// CHECK-INST: add za.d[w11, 7, vgx4], { z28.d - z31.d }
+// CHECK-ENCODING: [0x97,0x7f,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17f97 <unknown>
+
+add za.d[w11, 7], {z28.d - z31.d} // 11000001-11100001-01111111-10010111
+// CHECK-INST: add za.d[w11, 7, vgx4], { z28.d - z31.d }
+// CHECK-ENCODING: [0x97,0x7f,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17f97 <unknown>
+
+add za.d[w8, 5, vgx4], {z16.d - z19.d} // 11000001-11100001-00011110-00010101
+// CHECK-INST: add za.d[w8, 5, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x15,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11e15 <unknown>
+
+add za.d[w8, 5], {z16.d - z19.d} // 11000001-11100001-00011110-00010101
+// CHECK-INST: add za.d[w8, 5, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x15,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11e15 <unknown>
+
+add za.d[w8, 1, vgx4], {z0.d - z3.d} // 11000001-11100001-00011100-00010001
+// CHECK-INST: add za.d[w8, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x11,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11c11 <unknown>
+
+add za.d[w8, 1], {z0.d - z3.d} // 11000001-11100001-00011100-00010001
+// CHECK-INST: add za.d[w8, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x11,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11c11 <unknown>
+
+add za.d[w10, 0, vgx4], {z16.d - z19.d} // 11000001-11100001-01011110-00010000
+// CHECK-INST: add za.d[w10, 0, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x10,0x5e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e15e10 <unknown>
+
+add za.d[w10, 0], {z16.d - z19.d} // 11000001-11100001-01011110-00010000
+// CHECK-INST: add za.d[w10, 0, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x10,0x5e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e15e10 <unknown>
+
+add za.d[w8, 0, vgx4], {z12.d - z15.d} // 11000001-11100001-00011101-10010000
+// CHECK-INST: add za.d[w8, 0, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x90,0x1d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11d90 <unknown>
+
+add za.d[w8, 0], {z12.d - z15.d} // 11000001-11100001-00011101-10010000
+// CHECK-INST: add za.d[w8, 0, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x90,0x1d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11d90 <unknown>
+
+add za.d[w10, 1, vgx4], {z0.d - z3.d} // 11000001-11100001-01011100-00010001
+// CHECK-INST: add za.d[w10, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x11,0x5c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e15c11 <unknown>
+
+add za.d[w10, 1], {z0.d - z3.d} // 11000001-11100001-01011100-00010001
+// CHECK-INST: add za.d[w10, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x11,0x5c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e15c11 <unknown>
+
+add za.d[w8, 5, vgx4], {z20.d - z23.d} // 11000001-11100001-00011110-10010101
+// CHECK-INST: add za.d[w8, 5, vgx4], { z20.d - z23.d }
+// CHECK-ENCODING: [0x95,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11e95 <unknown>
+
+add za.d[w8, 5], {z20.d - z23.d} // 11000001-11100001-00011110-10010101
+// CHECK-INST: add za.d[w8, 5, vgx4], { z20.d - z23.d }
+// CHECK-ENCODING: [0x95,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11e95 <unknown>
+
+add za.d[w11, 2, vgx4], {z8.d - z11.d} // 11000001-11100001-01111101-00010010
+// CHECK-INST: add za.d[w11, 2, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x12,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17d12 <unknown>
+
+add za.d[w11, 2], {z8.d - z11.d} // 11000001-11100001-01111101-00010010
+// CHECK-INST: add za.d[w11, 2, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x12,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17d12 <unknown>
+
+add za.d[w9, 7, vgx4], {z12.d - z15.d} // 11000001-11100001-00111101-10010111
+// CHECK-INST: add za.d[w9, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x97,0x3d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e13d97 <unknown>
+
+add za.d[w9, 7], {z12.d - z15.d} // 11000001-11100001-00111101-10010111
+// CHECK-INST: add za.d[w9, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x97,0x3d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e13d97 <unknown>
+
+
add za.d[w8, 0, vgx4], {z0.d - z3.d}, z0.d // 11000001-01110000-00011000-00010000
// CHECK-INST: add za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d
// CHECK-ENCODING: [0x10,0x18,0x70,0xc1]
@@ -1348,7 +1919,7 @@ add {z28.d-z31.d}, {z28.d-z31.d}, z15.d // 11000001-11101111-10101011-00011
// CHECK-UNKNOWN: c1efab1c <unknown>
-add za.d[w8, 0, vgx4], {z0.d-z3.d}, {z0.d-z3.d} // 11000001-11100001-00011000-00010000
+add za.d[w8, 0, vgx4], {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100001-00011000-00010000
// CHECK-INST: add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
// CHECK-ENCODING: [0x10,0x18,0xe1,0xc1]
// CHECK-ERROR: instruction requires: sme2
diff --git a/llvm/test/MC/AArch64/SME2/fadd-diagnostics.s b/llvm/test/MC/AArch64/SME2/fadd-diagnostics.s
new file mode 100644
index 000000000000..800fa17170a6
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fadd-diagnostics.s
@@ -0,0 +1,46 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-f64f64 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Out of range index offset
+
+fadd za.d[w8, 8, vgx2], {z0.d, z1.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: fadd za.d[w8, 8, vgx2], {z0.d, z1.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadd za.s[w8, -1, vgx4], {z0.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: fadd za.s[w8, -1, vgx4], {z0.s-z3.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+fadd za.d[w7, 7, vgx4], {z0.d-z3.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: fadd za.d[w7, 7, vgx4], {z0.d-z3.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadd za.s[w12, 7, vgx2], {z0.s, z1.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: fadd za.s[w12, 7, vgx2], {z0.s, z1.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+fadd za.d[w8, 0, vgx4], {z0.d-z4.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: fadd za.d[w8, 0, vgx4], {z0.d-z4.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadd za.s[w8, 0, vgx2], {z1.s-z2.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: fadd za.s[w8, 0, vgx2], {z1.s-z2.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadd za.s[w8, 0, vgx4], {z1.s-z4.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: fadd za.s[w8, 0, vgx4], {z1.s-z4.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
diff --git a/llvm/test/MC/AArch64/SME2/fadd.s b/llvm/test/MC/AArch64/SME2/fadd.s
new file mode 100644
index 000000000000..e5c359f93cae
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fadd.s
@@ -0,0 +1,593 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-f64f64 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-f64f64 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2,+sme-f64f64 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-f64f64 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-f64f64 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+sme-f64f64 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fadd za.d[w8, 0, vgx2], {z0.d, z1.d} // 11000001-11100000-00011100-00000000
+// CHECK-INST: fadd za.d[w8, 0, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x00,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01c00 <unknown>
+
+fadd za.d[w8, 0], {z0.d, z1.d} // 11000001-11100000-00011100-00000000
+// CHECK-INST: fadd za.d[w8, 0, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x00,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01c00 <unknown>
+
+fadd za.d[w10, 5, vgx2], {z10.d, z11.d} // 11000001-11100000-01011101-01000101
+// CHECK-INST: fadd za.d[w10, 5, vgx2], { z10.d, z11.d }
+// CHECK-ENCODING: [0x45,0x5d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e05d45 <unknown>
+
+fadd za.d[w10, 5], {z10.d, z11.d} // 11000001-11100000-01011101-01000101
+// CHECK-INST: fadd za.d[w10, 5, vgx2], { z10.d, z11.d }
+// CHECK-ENCODING: [0x45,0x5d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e05d45 <unknown>
+
+fadd za.d[w11, 7, vgx2], {z12.d, z13.d} // 11000001-11100000-01111101-10000111
+// CHECK-INST: fadd za.d[w11, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x87,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e07d87 <unknown>
+
+fadd za.d[w11, 7], {z12.d, z13.d} // 11000001-11100000-01111101-10000111
+// CHECK-INST: fadd za.d[w11, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x87,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e07d87 <unknown>
+
+fadd za.d[w11, 7, vgx2], {z30.d, z31.d} // 11000001-11100000-01111111-11000111
+// CHECK-INST: fadd za.d[w11, 7, vgx2], { z30.d, z31.d }
+// CHECK-ENCODING: [0xc7,0x7f,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e07fc7 <unknown>
+
+fadd za.d[w11, 7], {z30.d, z31.d} // 11000001-11100000-01111111-11000111
+// CHECK-INST: fadd za.d[w11, 7, vgx2], { z30.d, z31.d }
+// CHECK-ENCODING: [0xc7,0x7f,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e07fc7 <unknown>
+
+fadd za.d[w8, 5, vgx2], {z16.d, z17.d} // 11000001-11100000-00011110-00000101
+// CHECK-INST: fadd za.d[w8, 5, vgx2], { z16.d, z17.d }
+// CHECK-ENCODING: [0x05,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01e05 <unknown>
+
+fadd za.d[w8, 5], {z16.d, z17.d} // 11000001-11100000-00011110-00000101
+// CHECK-INST: fadd za.d[w8, 5, vgx2], { z16.d, z17.d }
+// CHECK-ENCODING: [0x05,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01e05 <unknown>
+
+fadd za.d[w8, 1, vgx2], {z0.d, z1.d} // 11000001-11100000-00011100-00000001
+// CHECK-INST: fadd za.d[w8, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x01,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01c01 <unknown>
+
+fadd za.d[w8, 1], {z0.d, z1.d} // 11000001-11100000-00011100-00000001
+// CHECK-INST: fadd za.d[w8, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x01,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01c01 <unknown>
+
+fadd za.d[w10, 0, vgx2], {z18.d, z19.d} // 11000001-11100000-01011110-01000000
+// CHECK-INST: fadd za.d[w10, 0, vgx2], { z18.d, z19.d }
+// CHECK-ENCODING: [0x40,0x5e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e05e40 <unknown>
+
+fadd za.d[w10, 0], {z18.d, z19.d} // 11000001-11100000-01011110-01000000
+// CHECK-INST: fadd za.d[w10, 0, vgx2], { z18.d, z19.d }
+// CHECK-ENCODING: [0x40,0x5e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e05e40 <unknown>
+
+fadd za.d[w8, 0, vgx2], {z12.d, z13.d} // 11000001-11100000-00011101-10000000
+// CHECK-INST: fadd za.d[w8, 0, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x80,0x1d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01d80 <unknown>
+
+fadd za.d[w8, 0], {z12.d, z13.d} // 11000001-11100000-00011101-10000000
+// CHECK-INST: fadd za.d[w8, 0, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x80,0x1d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01d80 <unknown>
+
+fadd za.d[w10, 1, vgx2], {z0.d, z1.d} // 11000001-11100000-01011100-00000001
+// CHECK-INST: fadd za.d[w10, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x01,0x5c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e05c01 <unknown>
+
+fadd za.d[w10, 1], {z0.d, z1.d} // 11000001-11100000-01011100-00000001
+// CHECK-INST: fadd za.d[w10, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x01,0x5c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e05c01 <unknown>
+
+fadd za.d[w8, 5, vgx2], {z22.d, z23.d} // 11000001-11100000-00011110-11000101
+// CHECK-INST: fadd za.d[w8, 5, vgx2], { z22.d, z23.d }
+// CHECK-ENCODING: [0xc5,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01ec5 <unknown>
+
+fadd za.d[w8, 5], {z22.d, z23.d} // 11000001-11100000-00011110-11000101
+// CHECK-INST: fadd za.d[w8, 5, vgx2], { z22.d, z23.d }
+// CHECK-ENCODING: [0xc5,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01ec5 <unknown>
+
+fadd za.d[w11, 2, vgx2], {z8.d, z9.d} // 11000001-11100000-01111101-00000010
+// CHECK-INST: fadd za.d[w11, 2, vgx2], { z8.d, z9.d }
+// CHECK-ENCODING: [0x02,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e07d02 <unknown>
+
+fadd za.d[w11, 2], {z8.d, z9.d} // 11000001-11100000-01111101-00000010
+// CHECK-INST: fadd za.d[w11, 2, vgx2], { z8.d, z9.d }
+// CHECK-ENCODING: [0x02,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e07d02 <unknown>
+
+fadd za.d[w9, 7, vgx2], {z12.d, z13.d} // 11000001-11100000-00111101-10000111
+// CHECK-INST: fadd za.d[w9, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x87,0x3d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e03d87 <unknown>
+
+fadd za.d[w9, 7], {z12.d, z13.d} // 11000001-11100000-00111101-10000111
+// CHECK-INST: fadd za.d[w9, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x87,0x3d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e03d87 <unknown>
+
+
+fadd za.s[w8, 0, vgx2], {z0.s, z1.s} // 11000001-10100000-00011100-00000000
+// CHECK-INST: fadd za.s[w8, 0, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c00 <unknown>
+
+fadd za.s[w8, 0], {z0.s, z1.s} // 11000001-10100000-00011100-00000000
+// CHECK-INST: fadd za.s[w8, 0, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c00 <unknown>
+
+fadd za.s[w10, 5, vgx2], {z10.s, z11.s} // 11000001-10100000-01011101-01000101
+// CHECK-INST: fadd za.s[w10, 5, vgx2], { z10.s, z11.s }
+// CHECK-ENCODING: [0x45,0x5d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05d45 <unknown>
+
+fadd za.s[w10, 5], {z10.s, z11.s} // 11000001-10100000-01011101-01000101
+// CHECK-INST: fadd za.s[w10, 5, vgx2], { z10.s, z11.s }
+// CHECK-ENCODING: [0x45,0x5d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05d45 <unknown>
+
+fadd za.s[w11, 7, vgx2], {z12.s, z13.s} // 11000001-10100000-01111101-10000111
+// CHECK-INST: fadd za.s[w11, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x87,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d87 <unknown>
+
+fadd za.s[w11, 7], {z12.s, z13.s} // 11000001-10100000-01111101-10000111
+// CHECK-INST: fadd za.s[w11, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x87,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d87 <unknown>
+
+fadd za.s[w11, 7, vgx2], {z30.s, z31.s} // 11000001-10100000-01111111-11000111
+// CHECK-INST: fadd za.s[w11, 7, vgx2], { z30.s, z31.s }
+// CHECK-ENCODING: [0xc7,0x7f,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07fc7 <unknown>
+
+fadd za.s[w11, 7], {z30.s, z31.s} // 11000001-10100000-01111111-11000111
+// CHECK-INST: fadd za.s[w11, 7, vgx2], { z30.s, z31.s }
+// CHECK-ENCODING: [0xc7,0x7f,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07fc7 <unknown>
+
+fadd za.s[w8, 5, vgx2], {z16.s, z17.s} // 11000001-10100000-00011110-00000101
+// CHECK-INST: fadd za.s[w8, 5, vgx2], { z16.s, z17.s }
+// CHECK-ENCODING: [0x05,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01e05 <unknown>
+
+fadd za.s[w8, 5], {z16.s, z17.s} // 11000001-10100000-00011110-00000101
+// CHECK-INST: fadd za.s[w8, 5, vgx2], { z16.s, z17.s }
+// CHECK-ENCODING: [0x05,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01e05 <unknown>
+
+fadd za.s[w8, 1, vgx2], {z0.s, z1.s} // 11000001-10100000-00011100-00000001
+// CHECK-INST: fadd za.s[w8, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x01,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c01 <unknown>
+
+fadd za.s[w8, 1], {z0.s, z1.s} // 11000001-10100000-00011100-00000001
+// CHECK-INST: fadd za.s[w8, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x01,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c01 <unknown>
+
+fadd za.s[w10, 0, vgx2], {z18.s, z19.s} // 11000001-10100000-01011110-01000000
+// CHECK-INST: fadd za.s[w10, 0, vgx2], { z18.s, z19.s }
+// CHECK-ENCODING: [0x40,0x5e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05e40 <unknown>
+
+fadd za.s[w10, 0], {z18.s, z19.s} // 11000001-10100000-01011110-01000000
+// CHECK-INST: fadd za.s[w10, 0, vgx2], { z18.s, z19.s }
+// CHECK-ENCODING: [0x40,0x5e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05e40 <unknown>
+
+fadd za.s[w8, 0, vgx2], {z12.s, z13.s} // 11000001-10100000-00011101-10000000
+// CHECK-INST: fadd za.s[w8, 0, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x80,0x1d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01d80 <unknown>
+
+fadd za.s[w8, 0], {z12.s, z13.s} // 11000001-10100000-00011101-10000000
+// CHECK-INST: fadd za.s[w8, 0, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x80,0x1d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01d80 <unknown>
+
+fadd za.s[w10, 1, vgx2], {z0.s, z1.s} // 11000001-10100000-01011100-00000001
+// CHECK-INST: fadd za.s[w10, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x01,0x5c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05c01 <unknown>
+
+fadd za.s[w10, 1], {z0.s, z1.s} // 11000001-10100000-01011100-00000001
+// CHECK-INST: fadd za.s[w10, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x01,0x5c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05c01 <unknown>
+
+fadd za.s[w8, 5, vgx2], {z22.s, z23.s} // 11000001-10100000-00011110-11000101
+// CHECK-INST: fadd za.s[w8, 5, vgx2], { z22.s, z23.s }
+// CHECK-ENCODING: [0xc5,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01ec5 <unknown>
+
+fadd za.s[w8, 5], {z22.s, z23.s} // 11000001-10100000-00011110-11000101
+// CHECK-INST: fadd za.s[w8, 5, vgx2], { z22.s, z23.s }
+// CHECK-ENCODING: [0xc5,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01ec5 <unknown>
+
+fadd za.s[w11, 2, vgx2], {z8.s, z9.s} // 11000001-10100000-01111101-00000010
+// CHECK-INST: fadd za.s[w11, 2, vgx2], { z8.s, z9.s }
+// CHECK-ENCODING: [0x02,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d02 <unknown>
+
+fadd za.s[w11, 2], {z8.s, z9.s} // 11000001-10100000-01111101-00000010
+// CHECK-INST: fadd za.s[w11, 2, vgx2], { z8.s, z9.s }
+// CHECK-ENCODING: [0x02,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d02 <unknown>
+
+fadd za.s[w9, 7, vgx2], {z12.s, z13.s} // 11000001-10100000-00111101-10000111
+// CHECK-INST: fadd za.s[w9, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x87,0x3d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a03d87 <unknown>
+
+fadd za.s[w9, 7], {z12.s, z13.s} // 11000001-10100000-00111101-10000111
+// CHECK-INST: fadd za.s[w9, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x87,0x3d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a03d87 <unknown>
+
+
+fadd za.d[w8, 0, vgx4], {z0.d - z3.d} // 11000001-11100001-00011100-00000000
+// CHECK-INST: fadd za.d[w8, 0, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x00,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11c00 <unknown>
+
+fadd za.d[w8, 0], {z0.d - z3.d} // 11000001-11100001-00011100-00000000
+// CHECK-INST: fadd za.d[w8, 0, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x00,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11c00 <unknown>
+
+fadd za.d[w10, 5, vgx4], {z8.d - z11.d} // 11000001-11100001-01011101-00000101
+// CHECK-INST: fadd za.d[w10, 5, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x05,0x5d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e15d05 <unknown>
+
+fadd za.d[w10, 5], {z8.d - z11.d} // 11000001-11100001-01011101-00000101
+// CHECK-INST: fadd za.d[w10, 5, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x05,0x5d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e15d05 <unknown>
+
+fadd za.d[w11, 7, vgx4], {z12.d - z15.d} // 11000001-11100001-01111101-10000111
+// CHECK-INST: fadd za.d[w11, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x87,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e17d87 <unknown>
+
+fadd za.d[w11, 7], {z12.d - z15.d} // 11000001-11100001-01111101-10000111
+// CHECK-INST: fadd za.d[w11, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x87,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e17d87 <unknown>
+
+fadd za.d[w11, 7, vgx4], {z28.d - z31.d} // 11000001-11100001-01111111-10000111
+// CHECK-INST: fadd za.d[w11, 7, vgx4], { z28.d - z31.d }
+// CHECK-ENCODING: [0x87,0x7f,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e17f87 <unknown>
+
+fadd za.d[w11, 7], {z28.d - z31.d} // 11000001-11100001-01111111-10000111
+// CHECK-INST: fadd za.d[w11, 7, vgx4], { z28.d - z31.d }
+// CHECK-ENCODING: [0x87,0x7f,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e17f87 <unknown>
+
+fadd za.d[w8, 5, vgx4], {z16.d - z19.d} // 11000001-11100001-00011110-00000101
+// CHECK-INST: fadd za.d[w8, 5, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x05,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11e05 <unknown>
+
+fadd za.d[w8, 5], {z16.d - z19.d} // 11000001-11100001-00011110-00000101
+// CHECK-INST: fadd za.d[w8, 5, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x05,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11e05 <unknown>
+
+fadd za.d[w8, 1, vgx4], {z0.d - z3.d} // 11000001-11100001-00011100-00000001
+// CHECK-INST: fadd za.d[w8, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x01,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11c01 <unknown>
+
+fadd za.d[w8, 1], {z0.d - z3.d} // 11000001-11100001-00011100-00000001
+// CHECK-INST: fadd za.d[w8, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x01,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11c01 <unknown>
+
+fadd za.d[w10, 0, vgx4], {z16.d - z19.d} // 11000001-11100001-01011110-00000000
+// CHECK-INST: fadd za.d[w10, 0, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x00,0x5e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e15e00 <unknown>
+
+fadd za.d[w10, 0], {z16.d - z19.d} // 11000001-11100001-01011110-00000000
+// CHECK-INST: fadd za.d[w10, 0, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x00,0x5e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e15e00 <unknown>
+
+fadd za.d[w8, 0, vgx4], {z12.d - z15.d} // 11000001-11100001-00011101-10000000
+// CHECK-INST: fadd za.d[w8, 0, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x80,0x1d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11d80 <unknown>
+
+fadd za.d[w8, 0], {z12.d - z15.d} // 11000001-11100001-00011101-10000000
+// CHECK-INST: fadd za.d[w8, 0, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x80,0x1d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11d80 <unknown>
+
+fadd za.d[w10, 1, vgx4], {z0.d - z3.d} // 11000001-11100001-01011100-00000001
+// CHECK-INST: fadd za.d[w10, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x01,0x5c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e15c01 <unknown>
+
+fadd za.d[w10, 1], {z0.d - z3.d} // 11000001-11100001-01011100-00000001
+// CHECK-INST: fadd za.d[w10, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x01,0x5c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e15c01 <unknown>
+
+fadd za.d[w8, 5, vgx4], {z20.d - z23.d} // 11000001-11100001-00011110-10000101
+// CHECK-INST: fadd za.d[w8, 5, vgx4], { z20.d - z23.d }
+// CHECK-ENCODING: [0x85,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11e85 <unknown>
+
+fadd za.d[w8, 5], {z20.d - z23.d} // 11000001-11100001-00011110-10000101
+// CHECK-INST: fadd za.d[w8, 5, vgx4], { z20.d - z23.d }
+// CHECK-ENCODING: [0x85,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11e85 <unknown>
+
+fadd za.d[w11, 2, vgx4], {z8.d - z11.d} // 11000001-11100001-01111101-00000010
+// CHECK-INST: fadd za.d[w11, 2, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x02,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e17d02 <unknown>
+
+fadd za.d[w11, 2], {z8.d - z11.d} // 11000001-11100001-01111101-00000010
+// CHECK-INST: fadd za.d[w11, 2, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x02,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e17d02 <unknown>
+
+fadd za.d[w9, 7, vgx4], {z12.d - z15.d} // 11000001-11100001-00111101-10000111
+// CHECK-INST: fadd za.d[w9, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x87,0x3d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e13d87 <unknown>
+
+fadd za.d[w9, 7], {z12.d - z15.d} // 11000001-11100001-00111101-10000111
+// CHECK-INST: fadd za.d[w9, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x87,0x3d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e13d87 <unknown>
+
+
+fadd za.s[w8, 0, vgx4], {z0.s - z3.s} // 11000001-10100001-00011100-00000000
+// CHECK-INST: fadd za.s[w8, 0, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c00 <unknown>
+
+fadd za.s[w8, 0], {z0.s - z3.s} // 11000001-10100001-00011100-00000000
+// CHECK-INST: fadd za.s[w8, 0, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c00 <unknown>
+
+fadd za.s[w10, 5, vgx4], {z8.s - z11.s} // 11000001-10100001-01011101-00000101
+// CHECK-INST: fadd za.s[w10, 5, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x05,0x5d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15d05 <unknown>
+
+fadd za.s[w10, 5], {z8.s - z11.s} // 11000001-10100001-01011101-00000101
+// CHECK-INST: fadd za.s[w10, 5, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x05,0x5d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15d05 <unknown>
+
+fadd za.s[w11, 7, vgx4], {z12.s - z15.s} // 11000001-10100001-01111101-10000111
+// CHECK-INST: fadd za.s[w11, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x87,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d87 <unknown>
+
+fadd za.s[w11, 7], {z12.s - z15.s} // 11000001-10100001-01111101-10000111
+// CHECK-INST: fadd za.s[w11, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x87,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d87 <unknown>
+
+fadd za.s[w11, 7, vgx4], {z28.s - z31.s} // 11000001-10100001-01111111-10000111
+// CHECK-INST: fadd za.s[w11, 7, vgx4], { z28.s - z31.s }
+// CHECK-ENCODING: [0x87,0x7f,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17f87 <unknown>
+
+fadd za.s[w11, 7], {z28.s - z31.s} // 11000001-10100001-01111111-10000111
+// CHECK-INST: fadd za.s[w11, 7, vgx4], { z28.s - z31.s }
+// CHECK-ENCODING: [0x87,0x7f,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17f87 <unknown>
+
+fadd za.s[w8, 5, vgx4], {z16.s - z19.s} // 11000001-10100001-00011110-00000101
+// CHECK-INST: fadd za.s[w8, 5, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x05,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e05 <unknown>
+
+fadd za.s[w8, 5], {z16.s - z19.s} // 11000001-10100001-00011110-00000101
+// CHECK-INST: fadd za.s[w8, 5, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x05,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e05 <unknown>
+
+fadd za.s[w8, 1, vgx4], {z0.s - z3.s} // 11000001-10100001-00011100-00000001
+// CHECK-INST: fadd za.s[w8, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x01,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c01 <unknown>
+
+fadd za.s[w8, 1], {z0.s - z3.s} // 11000001-10100001-00011100-00000001
+// CHECK-INST: fadd za.s[w8, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x01,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c01 <unknown>
+
+fadd za.s[w10, 0, vgx4], {z16.s - z19.s} // 11000001-10100001-01011110-00000000
+// CHECK-INST: fadd za.s[w10, 0, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x00,0x5e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15e00 <unknown>
+
+fadd za.s[w10, 0], {z16.s - z19.s} // 11000001-10100001-01011110-00000000
+// CHECK-INST: fadd za.s[w10, 0, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x00,0x5e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15e00 <unknown>
+
+fadd za.s[w8, 0, vgx4], {z12.s - z15.s} // 11000001-10100001-00011101-10000000
+// CHECK-INST: fadd za.s[w8, 0, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x80,0x1d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11d80 <unknown>
+
+fadd za.s[w8, 0], {z12.s - z15.s} // 11000001-10100001-00011101-10000000
+// CHECK-INST: fadd za.s[w8, 0, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x80,0x1d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11d80 <unknown>
+
+fadd za.s[w10, 1, vgx4], {z0.s - z3.s} // 11000001-10100001-01011100-00000001
+// CHECK-INST: fadd za.s[w10, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x01,0x5c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15c01 <unknown>
+
+fadd za.s[w10, 1], {z0.s - z3.s} // 11000001-10100001-01011100-00000001
+// CHECK-INST: fadd za.s[w10, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x01,0x5c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15c01 <unknown>
+
+fadd za.s[w8, 5, vgx4], {z20.s - z23.s} // 11000001-10100001-00011110-10000101
+// CHECK-INST: fadd za.s[w8, 5, vgx4], { z20.s - z23.s }
+// CHECK-ENCODING: [0x85,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e85 <unknown>
+
+fadd za.s[w8, 5], {z20.s - z23.s} // 11000001-10100001-00011110-10000101
+// CHECK-INST: fadd za.s[w8, 5, vgx4], { z20.s - z23.s }
+// CHECK-ENCODING: [0x85,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e85 <unknown>
+
+fadd za.s[w11, 2, vgx4], {z8.s - z11.s} // 11000001-10100001-01111101-00000010
+// CHECK-INST: fadd za.s[w11, 2, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x02,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d02 <unknown>
+
+fadd za.s[w11, 2], {z8.s - z11.s} // 11000001-10100001-01111101-00000010
+// CHECK-INST: fadd za.s[w11, 2, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x02,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d02 <unknown>
+
+fadd za.s[w9, 7, vgx4], {z12.s - z15.s} // 11000001-10100001-00111101-10000111
+// CHECK-INST: fadd za.s[w9, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x87,0x3d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a13d87 <unknown>
+
+fadd za.s[w9, 7], {z12.s - z15.s} // 11000001-10100001-00111101-10000111
+// CHECK-INST: fadd za.s[w9, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x87,0x3d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a13d87 <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/fsub-diagnostics.s b/llvm/test/MC/AArch64/SME2/fsub-diagnostics.s
new file mode 100644
index 000000000000..1ec07cc16746
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fsub-diagnostics.s
@@ -0,0 +1,46 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-f64f64 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Out of range index offset
+
+fsub za.d[w8, 8, vgx2], {z0.d, z1.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: fsub za.d[w8, 8, vgx2], {z0.d, z1.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fsub za.s[w8, -1, vgx4], {z0.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: fsub za.s[w8, -1, vgx4], {z0.s-z3.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+fsub za.d[w7, 7, vgx4], {z0.d-z3.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: fsub za.d[w7, 7, vgx4], {z0.d-z3.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fsub za.s[w12, 7, vgx2], {z0.s, z1.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: fsub za.s[w12, 7, vgx2], {z0.s, z1.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+fsub za.d[w8, 0, vgx4], {z0.d-z4.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: fsub za.d[w8, 0, vgx4], {z0.d-z4.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fsub za.s[w8, 0, vgx2], {z1.s-z2.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: fsub za.s[w8, 0, vgx2], {z1.s-z2.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fsub za.s[w8, 0, vgx4], {z1.s-z4.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: fsub za.s[w8, 0, vgx4], {z1.s-z4.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
diff --git a/llvm/test/MC/AArch64/SME2/fsub.s b/llvm/test/MC/AArch64/SME2/fsub.s
new file mode 100644
index 000000000000..bc16059e38df
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fsub.s
@@ -0,0 +1,593 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-f64f64 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-f64f64 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2,+sme-f64f64 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-f64f64 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-f64f64 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+sme-f64f64 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fsub za.d[w8, 0, vgx2], {z0.d, z1.d} // 11000001-11100000-00011100-00001000
+// CHECK-INST: fsub za.d[w8, 0, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x08,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01c08 <unknown>
+
+fsub za.d[w8, 0], {z0.d, z1.d} // 11000001-11100000-00011100-00001000
+// CHECK-INST: fsub za.d[w8, 0, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x08,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01c08 <unknown>
+
+fsub za.d[w10, 5, vgx2], {z10.d, z11.d} // 11000001-11100000-01011101-01001101
+// CHECK-INST: fsub za.d[w10, 5, vgx2], { z10.d, z11.d }
+// CHECK-ENCODING: [0x4d,0x5d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e05d4d <unknown>
+
+fsub za.d[w10, 5], {z10.d, z11.d} // 11000001-11100000-01011101-01001101
+// CHECK-INST: fsub za.d[w10, 5, vgx2], { z10.d, z11.d }
+// CHECK-ENCODING: [0x4d,0x5d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e05d4d <unknown>
+
+fsub za.d[w11, 7, vgx2], {z12.d, z13.d} // 11000001-11100000-01111101-10001111
+// CHECK-INST: fsub za.d[w11, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x8f,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e07d8f <unknown>
+
+fsub za.d[w11, 7], {z12.d, z13.d} // 11000001-11100000-01111101-10001111
+// CHECK-INST: fsub za.d[w11, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x8f,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e07d8f <unknown>
+
+fsub za.d[w11, 7, vgx2], {z30.d, z31.d} // 11000001-11100000-01111111-11001111
+// CHECK-INST: fsub za.d[w11, 7, vgx2], { z30.d, z31.d }
+// CHECK-ENCODING: [0xcf,0x7f,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e07fcf <unknown>
+
+fsub za.d[w11, 7], {z30.d, z31.d} // 11000001-11100000-01111111-11001111
+// CHECK-INST: fsub za.d[w11, 7, vgx2], { z30.d, z31.d }
+// CHECK-ENCODING: [0xcf,0x7f,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e07fcf <unknown>
+
+fsub za.d[w8, 5, vgx2], {z16.d, z17.d} // 11000001-11100000-00011110-00001101
+// CHECK-INST: fsub za.d[w8, 5, vgx2], { z16.d, z17.d }
+// CHECK-ENCODING: [0x0d,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01e0d <unknown>
+
+fsub za.d[w8, 5], {z16.d, z17.d} // 11000001-11100000-00011110-00001101
+// CHECK-INST: fsub za.d[w8, 5, vgx2], { z16.d, z17.d }
+// CHECK-ENCODING: [0x0d,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01e0d <unknown>
+
+fsub za.d[w8, 1, vgx2], {z0.d, z1.d} // 11000001-11100000-00011100-00001001
+// CHECK-INST: fsub za.d[w8, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x09,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01c09 <unknown>
+
+fsub za.d[w8, 1], {z0.d, z1.d} // 11000001-11100000-00011100-00001001
+// CHECK-INST: fsub za.d[w8, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x09,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01c09 <unknown>
+
+fsub za.d[w10, 0, vgx2], {z18.d, z19.d} // 11000001-11100000-01011110-01001000
+// CHECK-INST: fsub za.d[w10, 0, vgx2], { z18.d, z19.d }
+// CHECK-ENCODING: [0x48,0x5e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e05e48 <unknown>
+
+fsub za.d[w10, 0], {z18.d, z19.d} // 11000001-11100000-01011110-01001000
+// CHECK-INST: fsub za.d[w10, 0, vgx2], { z18.d, z19.d }
+// CHECK-ENCODING: [0x48,0x5e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e05e48 <unknown>
+
+fsub za.d[w8, 0, vgx2], {z12.d, z13.d} // 11000001-11100000-00011101-10001000
+// CHECK-INST: fsub za.d[w8, 0, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x88,0x1d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01d88 <unknown>
+
+fsub za.d[w8, 0], {z12.d, z13.d} // 11000001-11100000-00011101-10001000
+// CHECK-INST: fsub za.d[w8, 0, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x88,0x1d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01d88 <unknown>
+
+fsub za.d[w10, 1, vgx2], {z0.d, z1.d} // 11000001-11100000-01011100-00001001
+// CHECK-INST: fsub za.d[w10, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x09,0x5c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e05c09 <unknown>
+
+fsub za.d[w10, 1], {z0.d, z1.d} // 11000001-11100000-01011100-00001001
+// CHECK-INST: fsub za.d[w10, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x09,0x5c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e05c09 <unknown>
+
+fsub za.d[w8, 5, vgx2], {z22.d, z23.d} // 11000001-11100000-00011110-11001101
+// CHECK-INST: fsub za.d[w8, 5, vgx2], { z22.d, z23.d }
+// CHECK-ENCODING: [0xcd,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01ecd <unknown>
+
+fsub za.d[w8, 5], {z22.d, z23.d} // 11000001-11100000-00011110-11001101
+// CHECK-INST: fsub za.d[w8, 5, vgx2], { z22.d, z23.d }
+// CHECK-ENCODING: [0xcd,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e01ecd <unknown>
+
+fsub za.d[w11, 2, vgx2], {z8.d, z9.d} // 11000001-11100000-01111101-00001010
+// CHECK-INST: fsub za.d[w11, 2, vgx2], { z8.d, z9.d }
+// CHECK-ENCODING: [0x0a,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e07d0a <unknown>
+
+fsub za.d[w11, 2], {z8.d, z9.d} // 11000001-11100000-01111101-00001010
+// CHECK-INST: fsub za.d[w11, 2, vgx2], { z8.d, z9.d }
+// CHECK-ENCODING: [0x0a,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e07d0a <unknown>
+
+fsub za.d[w9, 7, vgx2], {z12.d, z13.d} // 11000001-11100000-00111101-10001111
+// CHECK-INST: fsub za.d[w9, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x8f,0x3d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e03d8f <unknown>
+
+fsub za.d[w9, 7], {z12.d, z13.d} // 11000001-11100000-00111101-10001111
+// CHECK-INST: fsub za.d[w9, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x8f,0x3d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e03d8f <unknown>
+
+
+fsub za.s[w8, 0, vgx2], {z0.s, z1.s} // 11000001-10100000-00011100-00001000
+// CHECK-INST: fsub za.s[w8, 0, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x08,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c08 <unknown>
+
+fsub za.s[w8, 0], {z0.s, z1.s} // 11000001-10100000-00011100-00001000
+// CHECK-INST: fsub za.s[w8, 0, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x08,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c08 <unknown>
+
+fsub za.s[w10, 5, vgx2], {z10.s, z11.s} // 11000001-10100000-01011101-01001101
+// CHECK-INST: fsub za.s[w10, 5, vgx2], { z10.s, z11.s }
+// CHECK-ENCODING: [0x4d,0x5d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05d4d <unknown>
+
+fsub za.s[w10, 5], {z10.s, z11.s} // 11000001-10100000-01011101-01001101
+// CHECK-INST: fsub za.s[w10, 5, vgx2], { z10.s, z11.s }
+// CHECK-ENCODING: [0x4d,0x5d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05d4d <unknown>
+
+fsub za.s[w11, 7, vgx2], {z12.s, z13.s} // 11000001-10100000-01111101-10001111
+// CHECK-INST: fsub za.s[w11, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x8f,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d8f <unknown>
+
+fsub za.s[w11, 7], {z12.s, z13.s} // 11000001-10100000-01111101-10001111
+// CHECK-INST: fsub za.s[w11, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x8f,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d8f <unknown>
+
+fsub za.s[w11, 7, vgx2], {z30.s, z31.s} // 11000001-10100000-01111111-11001111
+// CHECK-INST: fsub za.s[w11, 7, vgx2], { z30.s, z31.s }
+// CHECK-ENCODING: [0xcf,0x7f,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07fcf <unknown>
+
+fsub za.s[w11, 7], {z30.s, z31.s} // 11000001-10100000-01111111-11001111
+// CHECK-INST: fsub za.s[w11, 7, vgx2], { z30.s, z31.s }
+// CHECK-ENCODING: [0xcf,0x7f,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07fcf <unknown>
+
+fsub za.s[w8, 5, vgx2], {z16.s, z17.s} // 11000001-10100000-00011110-00001101
+// CHECK-INST: fsub za.s[w8, 5, vgx2], { z16.s, z17.s }
+// CHECK-ENCODING: [0x0d,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01e0d <unknown>
+
+fsub za.s[w8, 5], {z16.s, z17.s} // 11000001-10100000-00011110-00001101
+// CHECK-INST: fsub za.s[w8, 5, vgx2], { z16.s, z17.s }
+// CHECK-ENCODING: [0x0d,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01e0d <unknown>
+
+fsub za.s[w8, 1, vgx2], {z0.s, z1.s} // 11000001-10100000-00011100-00001001
+// CHECK-INST: fsub za.s[w8, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x09,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c09 <unknown>
+
+fsub za.s[w8, 1], {z0.s, z1.s} // 11000001-10100000-00011100-00001001
+// CHECK-INST: fsub za.s[w8, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x09,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c09 <unknown>
+
+fsub za.s[w10, 0, vgx2], {z18.s, z19.s} // 11000001-10100000-01011110-01001000
+// CHECK-INST: fsub za.s[w10, 0, vgx2], { z18.s, z19.s }
+// CHECK-ENCODING: [0x48,0x5e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05e48 <unknown>
+
+fsub za.s[w10, 0], {z18.s, z19.s} // 11000001-10100000-01011110-01001000
+// CHECK-INST: fsub za.s[w10, 0, vgx2], { z18.s, z19.s }
+// CHECK-ENCODING: [0x48,0x5e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05e48 <unknown>
+
+fsub za.s[w8, 0, vgx2], {z12.s, z13.s} // 11000001-10100000-00011101-10001000
+// CHECK-INST: fsub za.s[w8, 0, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x88,0x1d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01d88 <unknown>
+
+fsub za.s[w8, 0], {z12.s, z13.s} // 11000001-10100000-00011101-10001000
+// CHECK-INST: fsub za.s[w8, 0, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x88,0x1d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01d88 <unknown>
+
+fsub za.s[w10, 1, vgx2], {z0.s, z1.s} // 11000001-10100000-01011100-00001001
+// CHECK-INST: fsub za.s[w10, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x09,0x5c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05c09 <unknown>
+
+fsub za.s[w10, 1], {z0.s, z1.s} // 11000001-10100000-01011100-00001001
+// CHECK-INST: fsub za.s[w10, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x09,0x5c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05c09 <unknown>
+
+fsub za.s[w8, 5, vgx2], {z22.s, z23.s} // 11000001-10100000-00011110-11001101
+// CHECK-INST: fsub za.s[w8, 5, vgx2], { z22.s, z23.s }
+// CHECK-ENCODING: [0xcd,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01ecd <unknown>
+
+fsub za.s[w8, 5], {z22.s, z23.s} // 11000001-10100000-00011110-11001101
+// CHECK-INST: fsub za.s[w8, 5, vgx2], { z22.s, z23.s }
+// CHECK-ENCODING: [0xcd,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01ecd <unknown>
+
+fsub za.s[w11, 2, vgx2], {z8.s, z9.s} // 11000001-10100000-01111101-00001010
+// CHECK-INST: fsub za.s[w11, 2, vgx2], { z8.s, z9.s }
+// CHECK-ENCODING: [0x0a,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d0a <unknown>
+
+fsub za.s[w11, 2], {z8.s, z9.s} // 11000001-10100000-01111101-00001010
+// CHECK-INST: fsub za.s[w11, 2, vgx2], { z8.s, z9.s }
+// CHECK-ENCODING: [0x0a,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d0a <unknown>
+
+fsub za.s[w9, 7, vgx2], {z12.s, z13.s} // 11000001-10100000-00111101-10001111
+// CHECK-INST: fsub za.s[w9, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x8f,0x3d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a03d8f <unknown>
+
+fsub za.s[w9, 7], {z12.s, z13.s} // 11000001-10100000-00111101-10001111
+// CHECK-INST: fsub za.s[w9, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x8f,0x3d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a03d8f <unknown>
+
+
+fsub za.d[w8, 0, vgx4], {z0.d - z3.d} // 11000001-11100001-00011100-00001000
+// CHECK-INST: fsub za.d[w8, 0, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x08,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11c08 <unknown>
+
+fsub za.d[w8, 0], {z0.d - z3.d} // 11000001-11100001-00011100-00001000
+// CHECK-INST: fsub za.d[w8, 0, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x08,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11c08 <unknown>
+
+fsub za.d[w10, 5, vgx4], {z8.d - z11.d} // 11000001-11100001-01011101-00001101
+// CHECK-INST: fsub za.d[w10, 5, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x0d,0x5d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e15d0d <unknown>
+
+fsub za.d[w10, 5], {z8.d - z11.d} // 11000001-11100001-01011101-00001101
+// CHECK-INST: fsub za.d[w10, 5, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x0d,0x5d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e15d0d <unknown>
+
+fsub za.d[w11, 7, vgx4], {z12.d - z15.d} // 11000001-11100001-01111101-10001111
+// CHECK-INST: fsub za.d[w11, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x8f,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e17d8f <unknown>
+
+fsub za.d[w11, 7], {z12.d - z15.d} // 11000001-11100001-01111101-10001111
+// CHECK-INST: fsub za.d[w11, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x8f,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e17d8f <unknown>
+
+fsub za.d[w11, 7, vgx4], {z28.d - z31.d} // 11000001-11100001-01111111-10001111
+// CHECK-INST: fsub za.d[w11, 7, vgx4], { z28.d - z31.d }
+// CHECK-ENCODING: [0x8f,0x7f,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e17f8f <unknown>
+
+fsub za.d[w11, 7], {z28.d - z31.d} // 11000001-11100001-01111111-10001111
+// CHECK-INST: fsub za.d[w11, 7, vgx4], { z28.d - z31.d }
+// CHECK-ENCODING: [0x8f,0x7f,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e17f8f <unknown>
+
+fsub za.d[w8, 5, vgx4], {z16.d - z19.d} // 11000001-11100001-00011110-00001101
+// CHECK-INST: fsub za.d[w8, 5, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x0d,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11e0d <unknown>
+
+fsub za.d[w8, 5], {z16.d - z19.d} // 11000001-11100001-00011110-00001101
+// CHECK-INST: fsub za.d[w8, 5, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x0d,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11e0d <unknown>
+
+fsub za.d[w8, 1, vgx4], {z0.d - z3.d} // 11000001-11100001-00011100-00001001
+// CHECK-INST: fsub za.d[w8, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x09,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11c09 <unknown>
+
+fsub za.d[w8, 1], {z0.d - z3.d} // 11000001-11100001-00011100-00001001
+// CHECK-INST: fsub za.d[w8, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x09,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11c09 <unknown>
+
+fsub za.d[w10, 0, vgx4], {z16.d - z19.d} // 11000001-11100001-01011110-00001000
+// CHECK-INST: fsub za.d[w10, 0, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x08,0x5e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e15e08 <unknown>
+
+fsub za.d[w10, 0], {z16.d - z19.d} // 11000001-11100001-01011110-00001000
+// CHECK-INST: fsub za.d[w10, 0, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x08,0x5e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e15e08 <unknown>
+
+fsub za.d[w8, 0, vgx4], {z12.d - z15.d} // 11000001-11100001-00011101-10001000
+// CHECK-INST: fsub za.d[w8, 0, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x88,0x1d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11d88 <unknown>
+
+fsub za.d[w8, 0], {z12.d - z15.d} // 11000001-11100001-00011101-10001000
+// CHECK-INST: fsub za.d[w8, 0, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x88,0x1d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11d88 <unknown>
+
+fsub za.d[w10, 1, vgx4], {z0.d - z3.d} // 11000001-11100001-01011100-00001001
+// CHECK-INST: fsub za.d[w10, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x09,0x5c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e15c09 <unknown>
+
+fsub za.d[w10, 1], {z0.d - z3.d} // 11000001-11100001-01011100-00001001
+// CHECK-INST: fsub za.d[w10, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x09,0x5c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e15c09 <unknown>
+
+fsub za.d[w8, 5, vgx4], {z20.d - z23.d} // 11000001-11100001-00011110-10001101
+// CHECK-INST: fsub za.d[w8, 5, vgx4], { z20.d - z23.d }
+// CHECK-ENCODING: [0x8d,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11e8d <unknown>
+
+fsub za.d[w8, 5], {z20.d - z23.d} // 11000001-11100001-00011110-10001101
+// CHECK-INST: fsub za.d[w8, 5, vgx4], { z20.d - z23.d }
+// CHECK-ENCODING: [0x8d,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e11e8d <unknown>
+
+fsub za.d[w11, 2, vgx4], {z8.d - z11.d} // 11000001-11100001-01111101-00001010
+// CHECK-INST: fsub za.d[w11, 2, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x0a,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e17d0a <unknown>
+
+fsub za.d[w11, 2], {z8.d - z11.d} // 11000001-11100001-01111101-00001010
+// CHECK-INST: fsub za.d[w11, 2, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x0a,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e17d0a <unknown>
+
+fsub za.d[w9, 7, vgx4], {z12.d - z15.d} // 11000001-11100001-00111101-10001111
+// CHECK-INST: fsub za.d[w9, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x8f,0x3d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e13d8f <unknown>
+
+fsub za.d[w9, 7], {z12.d - z15.d} // 11000001-11100001-00111101-10001111
+// CHECK-INST: fsub za.d[w9, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x8f,0x3d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sme-f64f64
+// CHECK-UNKNOWN: c1e13d8f <unknown>
+
+
+fsub za.s[w8, 0, vgx4], {z0.s - z3.s} // 11000001-10100001-00011100-00001000
+// CHECK-INST: fsub za.s[w8, 0, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x08,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c08 <unknown>
+
+fsub za.s[w8, 0], {z0.s - z3.s} // 11000001-10100001-00011100-00001000
+// CHECK-INST: fsub za.s[w8, 0, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x08,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c08 <unknown>
+
+fsub za.s[w10, 5, vgx4], {z8.s - z11.s} // 11000001-10100001-01011101-00001101
+// CHECK-INST: fsub za.s[w10, 5, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x0d,0x5d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15d0d <unknown>
+
+fsub za.s[w10, 5], {z8.s - z11.s} // 11000001-10100001-01011101-00001101
+// CHECK-INST: fsub za.s[w10, 5, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x0d,0x5d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15d0d <unknown>
+
+fsub za.s[w11, 7, vgx4], {z12.s - z15.s} // 11000001-10100001-01111101-10001111
+// CHECK-INST: fsub za.s[w11, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x8f,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d8f <unknown>
+
+fsub za.s[w11, 7], {z12.s - z15.s} // 11000001-10100001-01111101-10001111
+// CHECK-INST: fsub za.s[w11, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x8f,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d8f <unknown>
+
+fsub za.s[w11, 7, vgx4], {z28.s - z31.s} // 11000001-10100001-01111111-10001111
+// CHECK-INST: fsub za.s[w11, 7, vgx4], { z28.s - z31.s }
+// CHECK-ENCODING: [0x8f,0x7f,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17f8f <unknown>
+
+fsub za.s[w11, 7], {z28.s - z31.s} // 11000001-10100001-01111111-10001111
+// CHECK-INST: fsub za.s[w11, 7, vgx4], { z28.s - z31.s }
+// CHECK-ENCODING: [0x8f,0x7f,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17f8f <unknown>
+
+fsub za.s[w8, 5, vgx4], {z16.s - z19.s} // 11000001-10100001-00011110-00001101
+// CHECK-INST: fsub za.s[w8, 5, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x0d,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e0d <unknown>
+
+fsub za.s[w8, 5], {z16.s - z19.s} // 11000001-10100001-00011110-00001101
+// CHECK-INST: fsub za.s[w8, 5, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x0d,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e0d <unknown>
+
+fsub za.s[w8, 1, vgx4], {z0.s - z3.s} // 11000001-10100001-00011100-00001001
+// CHECK-INST: fsub za.s[w8, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x09,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c09 <unknown>
+
+fsub za.s[w8, 1], {z0.s - z3.s} // 11000001-10100001-00011100-00001001
+// CHECK-INST: fsub za.s[w8, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x09,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c09 <unknown>
+
+fsub za.s[w10, 0, vgx4], {z16.s - z19.s} // 11000001-10100001-01011110-00001000
+// CHECK-INST: fsub za.s[w10, 0, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x08,0x5e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15e08 <unknown>
+
+fsub za.s[w10, 0], {z16.s - z19.s} // 11000001-10100001-01011110-00001000
+// CHECK-INST: fsub za.s[w10, 0, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x08,0x5e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15e08 <unknown>
+
+fsub za.s[w8, 0, vgx4], {z12.s - z15.s} // 11000001-10100001-00011101-10001000
+// CHECK-INST: fsub za.s[w8, 0, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x88,0x1d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11d88 <unknown>
+
+fsub za.s[w8, 0], {z12.s - z15.s} // 11000001-10100001-00011101-10001000
+// CHECK-INST: fsub za.s[w8, 0, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x88,0x1d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11d88 <unknown>
+
+fsub za.s[w10, 1, vgx4], {z0.s - z3.s} // 11000001-10100001-01011100-00001001
+// CHECK-INST: fsub za.s[w10, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x09,0x5c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15c09 <unknown>
+
+fsub za.s[w10, 1], {z0.s - z3.s} // 11000001-10100001-01011100-00001001
+// CHECK-INST: fsub za.s[w10, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x09,0x5c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15c09 <unknown>
+
+fsub za.s[w8, 5, vgx4], {z20.s - z23.s} // 11000001-10100001-00011110-10001101
+// CHECK-INST: fsub za.s[w8, 5, vgx4], { z20.s - z23.s }
+// CHECK-ENCODING: [0x8d,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e8d <unknown>
+
+fsub za.s[w8, 5], {z20.s - z23.s} // 11000001-10100001-00011110-10001101
+// CHECK-INST: fsub za.s[w8, 5, vgx4], { z20.s - z23.s }
+// CHECK-ENCODING: [0x8d,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e8d <unknown>
+
+fsub za.s[w11, 2, vgx4], {z8.s - z11.s} // 11000001-10100001-01111101-00001010
+// CHECK-INST: fsub za.s[w11, 2, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x0a,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d0a <unknown>
+
+fsub za.s[w11, 2], {z8.s - z11.s} // 11000001-10100001-01111101-00001010
+// CHECK-INST: fsub za.s[w11, 2, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x0a,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d0a <unknown>
+
+fsub za.s[w9, 7, vgx4], {z12.s - z15.s} // 11000001-10100001-00111101-10001111
+// CHECK-INST: fsub za.s[w9, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x8f,0x3d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a13d8f <unknown>
+
+fsub za.s[w9, 7], {z12.s - z15.s} // 11000001-10100001-00111101-10001111
+// CHECK-INST: fsub za.s[w9, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x8f,0x3d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a13d8f <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/sub-diagnostics.s b/llvm/test/MC/AArch64/SME2/sub-diagnostics.s
index 4a7e7b20236f..e4d651f34622 100644
--- a/llvm/test/MC/AArch64/SME2/sub-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2/sub-diagnostics.s
@@ -13,6 +13,16 @@ sub za.d[w8, -1, vgx4], {z0.s-z3.s}, z0.s
// CHECK-NEXT: sub za.d[w8, -1, vgx4], {z0.s-z3.s}, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+sub za.d[w8, 8, vgx4], {z0.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: za.d[w8, 8, vgx4], {z0.s-z3.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sub za.d[w8, -1, vgx4], {z0.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: za.d[w8, -1, vgx4], {z0.s-z3.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector select register
@@ -34,6 +44,10 @@ sub za.h[w8, #0], {z0.h-z3.h}, z4.h
// CHECK-NEXT: sub za.h[w8, #0], {z0.h-z3.h}, z4.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+sub za.h[w8, 0, vgx2], {z0.s, z1.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .d
+// CHECK-NEXT: za.h[w8, 0, vgx2], {z0.s, z1.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector grouping
@@ -75,3 +89,4 @@ sub za.d[w11, 7], {z28.h - z31.h}, {z28.h - z31.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sub za.d[w11, 7], {z28.h - z31.h}, {z28.h - z31.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
diff --git a/llvm/test/MC/AArch64/SME2/sub.s b/llvm/test/MC/AArch64/SME2/sub.s
index f2474bd7b68f..43838ace114b 100644
--- a/llvm/test/MC/AArch64/SME2/sub.s
+++ b/llvm/test/MC/AArch64/SME2/sub.s
@@ -12,6 +12,151 @@
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+sub za.s[w8, 0, vgx2], {z0.s, z1.s} // 11000001-10100000-00011100-00011000
+// CHECK-INST: sub za.s[w8, 0, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x18,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c18 <unknown>
+
+sub za.s[w8, 0], {z0.s, z1.s} // 11000001-10100000-00011100-00011000
+// CHECK-INST: sub za.s[w8, 0, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x18,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c18 <unknown>
+
+sub za.s[w10, 5, vgx2], {z10.s, z11.s} // 11000001-10100000-01011101-01011101
+// CHECK-INST: sub za.s[w10, 5, vgx2], { z10.s, z11.s }
+// CHECK-ENCODING: [0x5d,0x5d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05d5d <unknown>
+
+sub za.s[w10, 5], {z10.s, z11.s} // 11000001-10100000-01011101-01011101
+// CHECK-INST: sub za.s[w10, 5, vgx2], { z10.s, z11.s }
+// CHECK-ENCODING: [0x5d,0x5d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05d5d <unknown>
+
+sub za.s[w11, 7, vgx2], {z12.s, z13.s} // 11000001-10100000-01111101-10011111
+// CHECK-INST: sub za.s[w11, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x9f,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d9f <unknown>
+
+sub za.s[w11, 7], {z12.s, z13.s} // 11000001-10100000-01111101-10011111
+// CHECK-INST: sub za.s[w11, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x9f,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d9f <unknown>
+
+sub za.s[w11, 7, vgx2], {z30.s, z31.s} // 11000001-10100000-01111111-11011111
+// CHECK-INST: sub za.s[w11, 7, vgx2], { z30.s, z31.s }
+// CHECK-ENCODING: [0xdf,0x7f,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07fdf <unknown>
+
+sub za.s[w11, 7], {z30.s, z31.s} // 11000001-10100000-01111111-11011111
+// CHECK-INST: sub za.s[w11, 7, vgx2], { z30.s, z31.s }
+// CHECK-ENCODING: [0xdf,0x7f,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07fdf <unknown>
+
+sub za.s[w8, 5, vgx2], {z16.s, z17.s} // 11000001-10100000-00011110-00011101
+// CHECK-INST: sub za.s[w8, 5, vgx2], { z16.s, z17.s }
+// CHECK-ENCODING: [0x1d,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01e1d <unknown>
+
+sub za.s[w8, 5], {z16.s, z17.s} // 11000001-10100000-00011110-00011101
+// CHECK-INST: sub za.s[w8, 5, vgx2], { z16.s, z17.s }
+// CHECK-ENCODING: [0x1d,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01e1d <unknown>
+
+sub za.s[w8, 1, vgx2], {z0.s, z1.s} // 11000001-10100000-00011100-00011001
+// CHECK-INST: sub za.s[w8, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x19,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c19 <unknown>
+
+sub za.s[w8, 1], {z0.s, z1.s} // 11000001-10100000-00011100-00011001
+// CHECK-INST: sub za.s[w8, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x19,0x1c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01c19 <unknown>
+
+sub za.s[w10, 0, vgx2], {z18.s, z19.s} // 11000001-10100000-01011110-01011000
+// CHECK-INST: sub za.s[w10, 0, vgx2], { z18.s, z19.s }
+// CHECK-ENCODING: [0x58,0x5e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05e58 <unknown>
+
+sub za.s[w10, 0], {z18.s, z19.s} // 11000001-10100000-01011110-01011000
+// CHECK-INST: sub za.s[w10, 0, vgx2], { z18.s, z19.s }
+// CHECK-ENCODING: [0x58,0x5e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05e58 <unknown>
+
+sub za.s[w8, 0, vgx2], {z12.s, z13.s} // 11000001-10100000-00011101-10011000
+// CHECK-INST: sub za.s[w8, 0, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x98,0x1d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01d98 <unknown>
+
+sub za.s[w8, 0], {z12.s, z13.s} // 11000001-10100000-00011101-10011000
+// CHECK-INST: sub za.s[w8, 0, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x98,0x1d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01d98 <unknown>
+
+sub za.s[w10, 1, vgx2], {z0.s, z1.s} // 11000001-10100000-01011100-00011001
+// CHECK-INST: sub za.s[w10, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x19,0x5c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05c19 <unknown>
+
+sub za.s[w10, 1], {z0.s, z1.s} // 11000001-10100000-01011100-00011001
+// CHECK-INST: sub za.s[w10, 1, vgx2], { z0.s, z1.s }
+// CHECK-ENCODING: [0x19,0x5c,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a05c19 <unknown>
+
+sub za.s[w8, 5, vgx2], {z22.s, z23.s} // 11000001-10100000-00011110-11011101
+// CHECK-INST: sub za.s[w8, 5, vgx2], { z22.s, z23.s }
+// CHECK-ENCODING: [0xdd,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01edd <unknown>
+
+sub za.s[w8, 5], {z22.s, z23.s} // 11000001-10100000-00011110-11011101
+// CHECK-INST: sub za.s[w8, 5, vgx2], { z22.s, z23.s }
+// CHECK-ENCODING: [0xdd,0x1e,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01edd <unknown>
+
+sub za.s[w11, 2, vgx2], {z8.s, z9.s} // 11000001-10100000-01111101-00011010
+// CHECK-INST: sub za.s[w11, 2, vgx2], { z8.s, z9.s }
+// CHECK-ENCODING: [0x1a,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d1a <unknown>
+
+sub za.s[w11, 2], {z8.s, z9.s} // 11000001-10100000-01111101-00011010
+// CHECK-INST: sub za.s[w11, 2, vgx2], { z8.s, z9.s }
+// CHECK-ENCODING: [0x1a,0x7d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07d1a <unknown>
+
+sub za.s[w9, 7, vgx2], {z12.s, z13.s} // 11000001-10100000-00111101-10011111
+// CHECK-INST: sub za.s[w9, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x9f,0x3d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a03d9f <unknown>
+
+sub za.s[w9, 7], {z12.s, z13.s} // 11000001-10100000-00111101-10011111
+// CHECK-INST: sub za.s[w9, 7, vgx2], { z12.s, z13.s }
+// CHECK-ENCODING: [0x9f,0x3d,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a03d9f <unknown>
+
+
sub za.s[w8, 0, vgx2], {z0.s, z1.s}, z0.s // 11000001, 00100000, 00011000, 00011000
// CHECK-INST: sub za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s
// CHECK-ENCODING: [0x18,0x18,0x20,0xc1]
@@ -302,6 +447,150 @@ sub za.s[w9, 7], {z12.s - z13.s}, {z10.s - z11.s} // 11000001-10101010-0011
// CHECK-UNKNOWN: c1aa399f <unknown>
+sub za.d[w8, 0, vgx2], {z0.d, z1.d} // 11000001-11100000-00011100-00011000
+// CHECK-INST: sub za.d[w8, 0, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x18,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01c18 <unknown>
+
+sub za.d[w8, 0], {z0.d, z1.d} // 11000001-11100000-00011100-00011000
+// CHECK-INST: sub za.d[w8, 0, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x18,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01c18 <unknown>
+
+sub za.d[w10, 5, vgx2], {z10.d, z11.d} // 11000001-11100000-01011101-01011101
+// CHECK-INST: sub za.d[w10, 5, vgx2], { z10.d, z11.d }
+// CHECK-ENCODING: [0x5d,0x5d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e05d5d <unknown>
+
+sub za.d[w10, 5], {z10.d, z11.d} // 11000001-11100000-01011101-01011101
+// CHECK-INST: sub za.d[w10, 5, vgx2], { z10.d, z11.d }
+// CHECK-ENCODING: [0x5d,0x5d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e05d5d <unknown>
+
+sub za.d[w11, 7, vgx2], {z12.d, z13.d} // 11000001-11100000-01111101-10011111
+// CHECK-INST: sub za.d[w11, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x9f,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07d9f <unknown>
+
+sub za.d[w11, 7], {z12.d, z13.d} // 11000001-11100000-01111101-10011111
+// CHECK-INST: sub za.d[w11, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x9f,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07d9f <unknown>
+
+sub za.d[w11, 7, vgx2], {z30.d, z31.d} // 11000001-11100000-01111111-11011111
+// CHECK-INST: sub za.d[w11, 7, vgx2], { z30.d, z31.d }
+// CHECK-ENCODING: [0xdf,0x7f,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07fdf <unknown>
+
+sub za.d[w11, 7], {z30.d, z31.d} // 11000001-11100000-01111111-11011111
+// CHECK-INST: sub za.d[w11, 7, vgx2], { z30.d, z31.d }
+// CHECK-ENCODING: [0xdf,0x7f,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07fdf <unknown>
+
+sub za.d[w8, 5, vgx2], {z16.d, z17.d} // 11000001-11100000-00011110-00011101
+// CHECK-INST: sub za.d[w8, 5, vgx2], { z16.d, z17.d }
+// CHECK-ENCODING: [0x1d,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01e1d <unknown>
+
+sub za.d[w8, 5], {z16.d, z17.d} // 11000001-11100000-00011110-00011101
+// CHECK-INST: sub za.d[w8, 5, vgx2], { z16.d, z17.d }
+// CHECK-ENCODING: [0x1d,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01e1d <unknown>
+
+sub za.d[w8, 1, vgx2], {z0.d, z1.d} // 11000001-11100000-00011100-00011001
+// CHECK-INST: sub za.d[w8, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x19,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01c19 <unknown>
+
+sub za.d[w8, 1], {z0.d, z1.d} // 11000001-11100000-00011100-00011001
+// CHECK-INST: sub za.d[w8, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x19,0x1c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01c19 <unknown>
+
+sub za.d[w10, 0, vgx2], {z18.d, z19.d} // 11000001-11100000-01011110-01011000
+// CHECK-INST: sub za.d[w10, 0, vgx2], { z18.d, z19.d }
+// CHECK-ENCODING: [0x58,0x5e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e05e58 <unknown>
+
+sub za.d[w10, 0], {z18.d, z19.d} // 11000001-11100000-01011110-01011000
+// CHECK-INST: sub za.d[w10, 0, vgx2], { z18.d, z19.d }
+// CHECK-ENCODING: [0x58,0x5e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e05e58 <unknown>
+
+sub za.d[w8, 0, vgx2], {z12.d, z13.d} // 11000001-11100000-00011101-10011000
+// CHECK-INST: sub za.d[w8, 0, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x98,0x1d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01d98 <unknown>
+
+sub za.d[w8, 0], {z12.d, z13.d} // 11000001-11100000-00011101-10011000
+// CHECK-INST: sub za.d[w8, 0, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x98,0x1d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01d98 <unknown>
+
+sub za.d[w10, 1, vgx2], {z0.d, z1.d} // 11000001-11100000-01011100-00011001
+// CHECK-INST: sub za.d[w10, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x19,0x5c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e05c19 <unknown>
+
+sub za.d[w10, 1], {z0.d, z1.d} // 11000001-11100000-01011100-00011001
+// CHECK-INST: sub za.d[w10, 1, vgx2], { z0.d, z1.d }
+// CHECK-ENCODING: [0x19,0x5c,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e05c19 <unknown>
+
+sub za.d[w8, 5, vgx2], {z22.d, z23.d} // 11000001-11100000-00011110-11011101
+// CHECK-INST: sub za.d[w8, 5, vgx2], { z22.d, z23.d }
+// CHECK-ENCODING: [0xdd,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01edd <unknown>
+
+sub za.d[w8, 5], {z22.d, z23.d} // 11000001-11100000-00011110-11011101
+// CHECK-INST: sub za.d[w8, 5, vgx2], { z22.d, z23.d }
+// CHECK-ENCODING: [0xdd,0x1e,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01edd <unknown>
+
+sub za.d[w11, 2, vgx2], {z8.d, z9.d} // 11000001-11100000-01111101-00011010
+// CHECK-INST: sub za.d[w11, 2, vgx2], { z8.d, z9.d }
+// CHECK-ENCODING: [0x1a,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07d1a <unknown>
+
+sub za.d[w11, 2], {z8.d, z9.d} // 11000001-11100000-01111101-00011010
+// CHECK-INST: sub za.d[w11, 2, vgx2], { z8.d, z9.d }
+// CHECK-ENCODING: [0x1a,0x7d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07d1a <unknown>
+
+sub za.d[w9, 7, vgx2], {z12.d, z13.d} // 11000001-11100000-00111101-10011111
+// CHECK-INST: sub za.d[w9, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x9f,0x3d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e03d9f <unknown>
+
+sub za.d[w9, 7], {z12.d, z13.d} // 11000001-11100000-00111101-10011111
+// CHECK-INST: sub za.d[w9, 7, vgx2], { z12.d, z13.d }
+// CHECK-ENCODING: [0x9f,0x3d,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e03d9f <unknown>
+
sub za.d[w8, 0, vgx2], {z0.d, z1.d}, z0.d // 11000001, 01100000, 00011000, 00011000
// CHECK-INST: sub za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d
// CHECK-ENCODING: [0x18,0x18,0x60,0xc1]
@@ -592,6 +881,151 @@ sub za.d[w9, 7], {z12.d - z13.d}, {z10.d - z11.d} // 11000001-11101010-0011
// CHECK-UNKNOWN: c1ea399f <unknown>
+sub za.s[w8, 0, vgx4], {z0.s - z3.s} // 11000001-10100001-00011100-00011000
+// CHECK-INST: sub za.s[w8, 0, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x18,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c18 <unknown>
+
+sub za.s[w8, 0], {z0.s - z3.s} // 11000001-10100001-00011100-00011000
+// CHECK-INST: sub za.s[w8, 0, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x18,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c18 <unknown>
+
+sub za.s[w10, 5, vgx4], {z8.s - z11.s} // 11000001-10100001-01011101-00011101
+// CHECK-INST: sub za.s[w10, 5, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x1d,0x5d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15d1d <unknown>
+
+sub za.s[w10, 5], {z8.s - z11.s} // 11000001-10100001-01011101-00011101
+// CHECK-INST: sub za.s[w10, 5, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x1d,0x5d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15d1d <unknown>
+
+sub za.s[w11, 7, vgx4], {z12.s - z15.s} // 11000001-10100001-01111101-10011111
+// CHECK-INST: sub za.s[w11, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x9f,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d9f <unknown>
+
+sub za.s[w11, 7], {z12.s - z15.s} // 11000001-10100001-01111101-10011111
+// CHECK-INST: sub za.s[w11, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x9f,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d9f <unknown>
+
+sub za.s[w11, 7, vgx4], {z28.s - z31.s} // 11000001-10100001-01111111-10011111
+// CHECK-INST: sub za.s[w11, 7, vgx4], { z28.s - z31.s }
+// CHECK-ENCODING: [0x9f,0x7f,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17f9f <unknown>
+
+sub za.s[w11, 7], {z28.s - z31.s} // 11000001-10100001-01111111-10011111
+// CHECK-INST: sub za.s[w11, 7, vgx4], { z28.s - z31.s }
+// CHECK-ENCODING: [0x9f,0x7f,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17f9f <unknown>
+
+sub za.s[w8, 5, vgx4], {z16.s - z19.s} // 11000001-10100001-00011110-00011101
+// CHECK-INST: sub za.s[w8, 5, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x1d,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e1d <unknown>
+
+sub za.s[w8, 5], {z16.s - z19.s} // 11000001-10100001-00011110-00011101
+// CHECK-INST: sub za.s[w8, 5, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x1d,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e1d <unknown>
+
+sub za.s[w8, 1, vgx4], {z0.s - z3.s} // 11000001-10100001-00011100-00011001
+// CHECK-INST: sub za.s[w8, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x19,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c19 <unknown>
+
+sub za.s[w8, 1], {z0.s - z3.s} // 11000001-10100001-00011100-00011001
+// CHECK-INST: sub za.s[w8, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x19,0x1c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11c19 <unknown>
+
+sub za.s[w10, 0, vgx4], {z16.s - z19.s} // 11000001-10100001-01011110-00011000
+// CHECK-INST: sub za.s[w10, 0, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x18,0x5e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15e18 <unknown>
+
+sub za.s[w10, 0], {z16.s - z19.s} // 11000001-10100001-01011110-00011000
+// CHECK-INST: sub za.s[w10, 0, vgx4], { z16.s - z19.s }
+// CHECK-ENCODING: [0x18,0x5e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15e18 <unknown>
+
+sub za.s[w8, 0, vgx4], {z12.s - z15.s} // 11000001-10100001-00011101-10011000
+// CHECK-INST: sub za.s[w8, 0, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x98,0x1d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11d98 <unknown>
+
+sub za.s[w8, 0], {z12.s - z15.s} // 11000001-10100001-00011101-10011000
+// CHECK-INST: sub za.s[w8, 0, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x98,0x1d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11d98 <unknown>
+
+sub za.s[w10, 1, vgx4], {z0.s - z3.s} // 11000001-10100001-01011100-00011001
+// CHECK-INST: sub za.s[w10, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x19,0x5c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15c19 <unknown>
+
+sub za.s[w10, 1], {z0.s - z3.s} // 11000001-10100001-01011100-00011001
+// CHECK-INST: sub za.s[w10, 1, vgx4], { z0.s - z3.s }
+// CHECK-ENCODING: [0x19,0x5c,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a15c19 <unknown>
+
+sub za.s[w8, 5, vgx4], {z20.s - z23.s} // 11000001-10100001-00011110-10011101
+// CHECK-INST: sub za.s[w8, 5, vgx4], { z20.s - z23.s }
+// CHECK-ENCODING: [0x9d,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e9d <unknown>
+
+sub za.s[w8, 5], {z20.s - z23.s} // 11000001-10100001-00011110-10011101
+// CHECK-INST: sub za.s[w8, 5, vgx4], { z20.s - z23.s }
+// CHECK-ENCODING: [0x9d,0x1e,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11e9d <unknown>
+
+sub za.s[w11, 2, vgx4], {z8.s - z11.s} // 11000001-10100001-01111101-00011010
+// CHECK-INST: sub za.s[w11, 2, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x1a,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d1a <unknown>
+
+sub za.s[w11, 2], {z8.s - z11.s} // 11000001-10100001-01111101-00011010
+// CHECK-INST: sub za.s[w11, 2, vgx4], { z8.s - z11.s }
+// CHECK-ENCODING: [0x1a,0x7d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17d1a <unknown>
+
+sub za.s[w9, 7, vgx4], {z12.s - z15.s} // 11000001-10100001-00111101-10011111
+// CHECK-INST: sub za.s[w9, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x9f,0x3d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a13d9f <unknown>
+
+sub za.s[w9, 7], {z12.s - z15.s} // 11000001-10100001-00111101-10011111
+// CHECK-INST: sub za.s[w9, 7, vgx4], { z12.s - z15.s }
+// CHECK-ENCODING: [0x9f,0x3d,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a13d9f <unknown>
+
+
sub za.s[w8, 0, vgx4], {z0.s - z3.s}, z0.s // 11000001-00110000-00011000-00011000
// CHECK-INST: sub za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
// CHECK-ENCODING: [0x18,0x18,0x30,0xc1]
@@ -882,6 +1316,150 @@ sub za.s[w9, 7], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-00111
// CHECK-UNKNOWN: c1a9399f <unknown>
+sub za.d[w8, 0, vgx4], {z0.d - z3.d} // 11000001-11100001-00011100-00011000
+// CHECK-INST: sub za.d[w8, 0, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x18,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11c18 <unknown>
+
+sub za.d[w8, 0], {z0.d - z3.d} // 11000001-11100001-00011100-00011000
+// CHECK-INST: sub za.d[w8, 0, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x18,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11c18 <unknown>
+
+sub za.d[w10, 5, vgx4], {z8.d - z11.d} // 11000001-11100001-01011101-00011101
+// CHECK-INST: sub za.d[w10, 5, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x1d,0x5d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e15d1d <unknown>
+
+sub za.d[w10, 5], {z8.d - z11.d} // 11000001-11100001-01011101-00011101
+// CHECK-INST: sub za.d[w10, 5, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x1d,0x5d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e15d1d <unknown>
+
+sub za.d[w11, 7, vgx4], {z12.d - z15.d} // 11000001-11100001-01111101-10011111
+// CHECK-INST: sub za.d[w11, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x9f,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17d9f <unknown>
+
+sub za.d[w11, 7], {z12.d - z15.d} // 11000001-11100001-01111101-10011111
+// CHECK-INST: sub za.d[w11, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x9f,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17d9f <unknown>
+
+sub za.d[w11, 7, vgx4], {z28.d - z31.d} // 11000001-11100001-01111111-10011111
+// CHECK-INST: sub za.d[w11, 7, vgx4], { z28.d - z31.d }
+// CHECK-ENCODING: [0x9f,0x7f,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17f9f <unknown>
+
+sub za.d[w11, 7], {z28.d - z31.d} // 11000001-11100001-01111111-10011111
+// CHECK-INST: sub za.d[w11, 7, vgx4], { z28.d - z31.d }
+// CHECK-ENCODING: [0x9f,0x7f,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17f9f <unknown>
+
+sub za.d[w8, 5, vgx4], {z16.d - z19.d} // 11000001-11100001-00011110-00011101
+// CHECK-INST: sub za.d[w8, 5, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x1d,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11e1d <unknown>
+
+sub za.d[w8, 5], {z16.d - z19.d} // 11000001-11100001-00011110-00011101
+// CHECK-INST: sub za.d[w8, 5, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x1d,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11e1d <unknown>
+
+sub za.d[w8, 1, vgx4], {z0.d - z3.d} // 11000001-11100001-00011100-00011001
+// CHECK-INST: sub za.d[w8, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x19,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11c19 <unknown>
+
+sub za.d[w8, 1], {z0.d - z3.d} // 11000001-11100001-00011100-00011001
+// CHECK-INST: sub za.d[w8, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x19,0x1c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11c19 <unknown>
+
+sub za.d[w10, 0, vgx4], {z16.d - z19.d} // 11000001-11100001-01011110-00011000
+// CHECK-INST: sub za.d[w10, 0, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x18,0x5e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e15e18 <unknown>
+
+sub za.d[w10, 0], {z16.d - z19.d} // 11000001-11100001-01011110-00011000
+// CHECK-INST: sub za.d[w10, 0, vgx4], { z16.d - z19.d }
+// CHECK-ENCODING: [0x18,0x5e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e15e18 <unknown>
+
+sub za.d[w8, 0, vgx4], {z12.d - z15.d} // 11000001-11100001-00011101-10011000
+// CHECK-INST: sub za.d[w8, 0, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x98,0x1d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11d98 <unknown>
+
+sub za.d[w8, 0], {z12.d - z15.d} // 11000001-11100001-00011101-10011000
+// CHECK-INST: sub za.d[w8, 0, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x98,0x1d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11d98 <unknown>
+
+sub za.d[w10, 1, vgx4], {z0.d - z3.d} // 11000001-11100001-01011100-00011001
+// CHECK-INST: sub za.d[w10, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x19,0x5c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e15c19 <unknown>
+
+sub za.d[w10, 1], {z0.d - z3.d} // 11000001-11100001-01011100-00011001
+// CHECK-INST: sub za.d[w10, 1, vgx4], { z0.d - z3.d }
+// CHECK-ENCODING: [0x19,0x5c,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e15c19 <unknown>
+
+sub za.d[w8, 5, vgx4], {z20.d - z23.d} // 11000001-11100001-00011110-10011101
+// CHECK-INST: sub za.d[w8, 5, vgx4], { z20.d - z23.d }
+// CHECK-ENCODING: [0x9d,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11e9d <unknown>
+
+sub za.d[w8, 5], {z20.d - z23.d} // 11000001-11100001-00011110-10011101
+// CHECK-INST: sub za.d[w8, 5, vgx4], { z20.d - z23.d }
+// CHECK-ENCODING: [0x9d,0x1e,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11e9d <unknown>
+
+sub za.d[w11, 2, vgx4], {z8.d - z11.d} // 11000001-11100001-01111101-00011010
+// CHECK-INST: sub za.d[w11, 2, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x1a,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17d1a <unknown>
+
+sub za.d[w11, 2], {z8.d - z11.d} // 11000001-11100001-01111101-00011010
+// CHECK-INST: sub za.d[w11, 2, vgx4], { z8.d - z11.d }
+// CHECK-ENCODING: [0x1a,0x7d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17d1a <unknown>
+
+sub za.d[w9, 7, vgx4], {z12.d - z15.d} // 11000001-11100001-00111101-10011111
+// CHECK-INST: sub za.d[w9, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x9f,0x3d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e13d9f <unknown>
+
+sub za.d[w9, 7], {z12.d - z15.d} // 11000001-11100001-00111101-10011111
+// CHECK-INST: sub za.d[w9, 7, vgx4], { z12.d - z15.d }
+// CHECK-ENCODING: [0x9f,0x3d,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e13d9f <unknown>
+
sub za.d[w8, 0, vgx4], {z0.d - z3.d}, z0.d // 11000001-01110000-00011000-00011000
// CHECK-INST: sub za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d
// CHECK-ENCODING: [0x18,0x18,0x70,0xc1]
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