[llvm] 9db12a4 - [AArch64]SME2 Multiple vector ternary int/float 2 and 4 registers
Caroline Concatto via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 20 10:44:57 PDT 2022
Author: Caroline Concatto
Date: 2022-10-20T18:44:22+01:00
New Revision: 9db12a45e472e502f92dcc0bf1396162003f5f09
URL: https://github.com/llvm/llvm-project/commit/9db12a45e472e502f92dcc0bf1396162003f5f09
DIFF: https://github.com/llvm/llvm-project/commit/9db12a45e472e502f92dcc0bf1396162003f5f09.diff
LOG: [AArch64]SME2 Multiple vector ternary int/float 2 and 4 registers
This patch adds the assembly/disassembly for the following instructions:
For INT:
ADD(array results, multiple vectors): Add multi-vector to multi-vector with ZA array vector results.
SUB(array results, multiple vectors): Subtract multi-vector from multi-vector with ZA array vector results.
For FP:
FMLA (multiple vectors): Multi-vector floating-point fused multiply-add.
FMLS (multiple vectors): Multi-vector floating-point fused multiply-subtract.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
This patch also adds a register operand to represent multiples of ZA multi-vectors.
They are:
ZZ_s_mul_r, ZZ_d_mul_r, ZZZZ_s_mul_r and ZZZZ_d_mul_r
and represent the Zn or Zm times 2 or 4 according to the vector group.
Depends on: D135455
Differential Revision: https://reviews.llvm.org/D135468
Added:
Modified:
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
llvm/lib/Target/AArch64/SMEInstrFormats.td
llvm/test/MC/AArch64/SME2/add-diagnostics.s
llvm/test/MC/AArch64/SME2/add.s
llvm/test/MC/AArch64/SME2/fmla-diagnostics.s
llvm/test/MC/AArch64/SME2/fmla.s
llvm/test/MC/AArch64/SME2/fmls-diagnostics.s
llvm/test/MC/AArch64/SME2/fmls.s
llvm/test/MC/AArch64/SME2/sub-diagnostics.s
llvm/test/MC/AArch64/SME2/sub.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index 5877819a49240..4fce066b90524 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -1076,6 +1076,45 @@ def ZZZZ_d : RegisterOperand<ZPR4, "printTypedVectorList<0,'d'>"> {
let ParserMatchClass = ZPRVectorList<64, 4>;
}
+// SME2 multiple-of-2 or 4 multi-vector operands
+def ZPR2Mul2 : RegisterClass<"AArch64", [untyped], 128, (add (decimate ZSeqPairs, 2))> {
+ let Size = 256;
+}
+
+def ZPR4Mul4 : RegisterClass<"AArch64", [untyped], 128, (add (decimate ZSeqQuads, 4))> {
+ let Size = 512;
+}
+
+class ZPRVectorListMul<int ElementWidth, int NumRegs> : ZPRVectorList<ElementWidth, NumRegs> {
+ let Name = "SVEVectorListMul" # NumRegs # "x" # ElementWidth;
+ let DiagnosticType = "Invalid" # Name;
+ let PredicateMethod =
+ "isTypedVectorListMultiple<RegKind::SVEDataVector, " # NumRegs # ", 0, "
+ # ElementWidth # ">";
+}
+
+let EncoderMethod = "EncodeRegAsMultipleOf<2>",
+ DecoderMethod = "DecodeZPR2Mul2RegisterClass" in {
+ def ZZ_s_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'s'>"> {
+ let ParserMatchClass = ZPRVectorListMul<32, 2>;
+ }
+
+ def ZZ_d_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'d'>"> {
+ let ParserMatchClass = ZPRVectorListMul<64, 2>;
+ }
+} // end let EncoderMethod/DecoderMethod
+
+let EncoderMethod = "EncodeRegAsMultipleOf<4>",
+ DecoderMethod = "DecodeZPR4Mul4RegisterClass" in {
+ def ZZZZ_s_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'s'>"> {
+ let ParserMatchClass = ZPRVectorListMul<32, 4>;
+ }
+
+ def ZZZZ_d_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'d'>"> {
+ let ParserMatchClass = ZPRVectorListMul<64, 4>;
+ }
+} // end let EncoderMethod/DecoderMethod
+
class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale,
bit ScaleAlwaysSame = 0b0> : AsmOperandClass {
let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index bd8b3b5275bd6..c966983e5bb61 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -247,32 +247,48 @@ defm PSEL_PPPRI : sve2_int_perm_sel_p<"psel", int_aarch64_sve_psel>;
// SME2 Instructions
//===----------------------------------------------------------------------===//
let Predicates = [HasSME2] in {
-defm ADD_VG2_M2ZZ_S : sme2_mla_add_sub_array_vg2_single_S<"add", 0b10>;
-defm ADD_VG4_M4ZZ_S : sme2_mla_add_sub_array_vg4_single_S<"add", 0b10>;
-
-defm SUB_VG2_M2ZZ_S : sme2_mla_add_sub_array_vg2_single_S<"sub", 0b11>;
-defm SUB_VG4_M4ZZ_S : sme2_mla_add_sub_array_vg4_single_S<"sub", 0b11>;
-
-defm FMLA_VG2_M2ZZ_S : sme2_mla_add_sub_array_vg2_single_S<"fmla", 0b00>;
-defm FMLA_VG4_M4ZZ_S : sme2_mla_add_sub_array_vg4_single_S<"fmla", 0b00>;
-
-defm FMLS_VG2_M2ZZ_S : sme2_mla_add_sub_array_vg2_single_S<"fmls", 0b01>;
-defm FMLS_VG4_M4ZZ_S : sme2_mla_add_sub_array_vg4_single_S<"fmls", 0b01>;
+defm ADD_VG2_M2ZZ_S : sme2_mla_add_sub_array_vg2_single_S<"add", 0b10>;
+defm ADD_VG4_M4ZZ_S : sme2_mla_add_sub_array_vg4_single_S<"add", 0b10>;
+defm ADD_VG2_M2Z2Z_S : sme2_mla_add_sub_array_vg2_multi_S<"add", 0b10>;
+defm ADD_VG4_M4Z4Z_S : sme2_mla_add_sub_array_vg4_multi_S<"add", 0b10>;
+
+defm SUB_VG2_M2ZZ_S : sme2_mla_add_sub_array_vg2_single_S<"sub", 0b11>;
+defm SUB_VG4_M4ZZ_S : sme2_mla_add_sub_array_vg4_single_S<"sub", 0b11>;
+defm SUB_VG2_M2Z2Z_S : sme2_mla_add_sub_array_vg2_multi_S<"sub", 0b11>;
+defm SUB_VG4_M4Z4Z_S : sme2_mla_add_sub_array_vg4_multi_S<"sub", 0b11>;
+
+defm FMLA_VG2_M2ZZ_S : sme2_mla_add_sub_array_vg2_single_S<"fmla", 0b00>;
+defm FMLA_VG4_M4ZZ_S : sme2_mla_add_sub_array_vg4_single_S<"fmla", 0b00>;
+defm FMLA_VG2_M2Z2Z_S : sme2_mla_add_sub_array_vg2_multi_S<"fmla", 0b00>;
+defm FMLA_VG4_M4Z4Z_S : sme2_mla_add_sub_array_vg4_multi_S<"fmla", 0b00>;
+
+defm FMLS_VG2_M2ZZ_S : sme2_mla_add_sub_array_vg2_single_S<"fmls", 0b01>;
+defm FMLS_VG4_M4ZZ_S : sme2_mla_add_sub_array_vg4_single_S<"fmls", 0b01>;
+defm FMLS_VG2_M2Z2Z_S : sme2_mla_add_sub_array_vg2_multi_S<"fmls", 0b01>;
+defm FMLS_VG4_M4Z4Z_S : sme2_mla_add_sub_array_vg4_multi_S<"fmls", 0b01>;
}
let Predicates = [HasSME2, HasSMEI16I64] in {
-defm ADD_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"add", 0b10>;
-defm ADD_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"add", 0b10>;
-
-defm SUB_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"sub", 0b11>;
-defm SUB_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"sub", 0b11>;
+defm ADD_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"add", 0b10>;
+defm ADD_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"add", 0b10>;
+defm ADD_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"add", 0b10>;
+defm ADD_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"add", 0b10>;
+
+defm SUB_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"sub", 0b11>;
+defm SUB_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"sub", 0b11>;
+defm SUB_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"sub", 0b11>;
+defm SUB_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"sub", 0b11>;
}
let Predicates = [HasSME2, HasSMEF64F64] in {
-defm FMLA_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"fmla", 0b00>;
-defm FMLA_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"fmla", 0b00>;
-
-defm FMLS_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"fmls", 0b01>;
-defm FMLS_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"fmls", 0b01>;
+defm FMLA_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"fmla", 0b00>;
+defm FMLA_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"fmla", 0b00>;
+defm FMLA_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"fmla", 0b00>;
+defm FMLA_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"fmla", 0b00>;
+
+defm FMLS_VG2_M2ZZ_D : sme2_mla_add_sub_array_vg2_single_D<"fmls", 0b01>;
+defm FMLS_VG4_M4ZZ_D : sme2_mla_add_sub_array_vg4_single_D<"fmls", 0b01>;
+defm FMLS_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"fmls", 0b01>;
+defm FMLS_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"fmls", 0b01>;
}
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index c89f1806638ff..2d0d9838c5c6e 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1312,6 +1312,18 @@ class AArch64Operand : public MCParsedAsmOperand {
return VectorList.NumElements == NumElements;
}
+ template <RegKind VectorKind, unsigned NumRegs, unsigned NumElements,
+ unsigned ElementWidth>
+ DiagnosticPredicate isTypedVectorListMultiple() const {
+ bool Res =
+ isTypedVectorList<VectorKind, NumRegs, NumElements, ElementWidth>();
+ if (!Res)
+ return DiagnosticPredicateTy::NoMatch;
+ if (((VectorList.RegNum - AArch64::Z0) % NumRegs) != 0)
+ return DiagnosticPredicateTy::NearMatch;
+ return DiagnosticPredicateTy::Match;
+ }
+
template <int Min, int Max>
DiagnosticPredicate isVectorIndex() const {
if (Kind != k_VectorIndex)
@@ -5514,6 +5526,16 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
return Error(Loc, "operand must be a register in range [w12, w15]");
case Match_InvalidMatrixIndexGPR32_8_11:
return Error(Loc, "operand must be a register in range [w8, w11]");
+ case Match_InvalidSVEVectorListMul2x32:
+ case Match_InvalidSVEVectorListMul2x64:
+ return Error(Loc, "Invalid vector list, expected list with 2 consecutive "
+ "SVE vectors, where the first vector is a multiple of 2 "
+ "and with matching element types");
+ case Match_InvalidSVEVectorListMul4x32:
+ case Match_InvalidSVEVectorListMul4x64:
+ return Error(Loc, "Invalid vector list, expected list with 4 consecutive "
+ "SVE vectors, where the first vector is a multiple of 4 "
+ "and with matching element types");
default:
llvm_unreachable("unexpected error code!");
}
@@ -6051,6 +6073,10 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidSVCR:
case Match_InvalidMatrixIndexGPR32_12_15:
case Match_InvalidMatrixIndexGPR32_8_11:
+ case Match_InvalidSVEVectorListMul2x32:
+ case Match_InvalidSVEVectorListMul2x64:
+ case Match_InvalidSVEVectorListMul4x32:
+ case Match_InvalidSVEVectorListMul4x64:
case Match_MSR:
case Match_MRS: {
if (ErrorInfo >= Operands.size())
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index eae84d27d430a..42f614c2b5546 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -117,6 +117,12 @@ static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder);
+static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder);
+static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder);
template <unsigned NumBitsForTile>
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
uint64_t Address,
@@ -625,6 +631,28 @@ static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
return Success;
}
+static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo * 2 > 30)
+ return Fail;
+ unsigned Register =
+ AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2);
+ Inst.addOperand(MCOperand::createReg(Register));
+ return Success;
+}
+
+static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo * 4 > 28)
+ return Fail;
+ unsigned Register =
+ AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
+ Inst.addOperand(MCOperand::createReg(Register));
+ return Success;
+}
+
static DecodeStatus
DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
uint64_t Address,
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
index cb0705df43bf6..228e244d934b6 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -185,6 +185,11 @@ class AArch64MCCodeEmitter : public MCCodeEmitter {
unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
+ template <unsigned Multiple>
+ uint32_t EncodeRegAsMultipleOf(const MCInst &MI, unsigned OpIdx,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
uint32_t EncodeMatrixTileListRegisterClass(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
@@ -517,6 +522,17 @@ AArch64MCCodeEmitter::getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
return MO.getImm() - 8;
}
+template <unsigned Multiple>
+uint32_t
+AArch64MCCodeEmitter::EncodeRegAsMultipleOf(const MCInst &MI, unsigned OpIdx,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ assert(llvm::isPowerOf2_32(Multiple) && "Multiple is not a power of 2");
+ auto RegOpnd = MI.getOperand(OpIdx).getReg();
+ unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd);
+ return RegVal / Multiple;
+}
+
uint32_t AArch64MCCodeEmitter::EncodeMatrixTileListRegisterClass(
const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index 655804e3b116e..69ba23d78c48a 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -1254,3 +1254,86 @@ multiclass sme2_mla_add_sub_array_vg4_single_D<string mnemonic, bits<2> op>{
(!cast<Instruction>(NAME) MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZZZ_d:$Zn, ZPR4b64:$Zm), 0>;
}
+//===----------------------------------------------------------------------===//
+// SME2 multiple vectors ternary INT/FP two and four registers
+class sme2_mla_add_sub_array_vg2_multi<bit sz, bits<2> op,
+ MatrixOperand matrix_ty,
+ RegisterOperand multi_vector_ty,
+ string mnemonic>
+ : I<(outs matrix_ty:$ZAd),
+ (ins matrix_ty:$_ZAd, MatrixIndexGPR32Op8_11:$Rv,
+ sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, multi_vector_ty:$Zm),
+ mnemonic, "\t$ZAd[$Rv, $imm3, vgx2], $Zn, $Zm",
+ "", []>, Sched<[]>{
+ bits<4> Zm;
+ bits<4> Zn;
+ bits<2> Rv;
+ bits<3> imm3;
+ let Inst{31-23} = 0b110000011;
+ let Inst{22} = sz;
+ let Inst{21} = 0b1;
+ let Inst{20-17} = Zm;
+ let Inst{16-15} = 0b00;
+ let Inst{14-13} = Rv;
+ let Inst{12-10} = 0b110;
+ let Inst{9-6} = Zn;
+ let Inst{5} = 0b0;
+ let Inst{4-3} = op;
+ let Inst{2-0} = imm3;
+ let Constraints = "$ZAd = $_ZAd";
+}
+
+multiclass sme2_mla_add_sub_array_vg2_multi_S<string mnemonic, bits<2> op>{
+ def NAME : sme2_mla_add_sub_array_vg2_multi<0b0, op, MatrixOp32, ZZ_s_mul_r, mnemonic>;
+
+ def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
+ (!cast<Instruction>(NAME) MatrixOp32:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZ_s_mul_r:$Zn, ZZ_s_mul_r:$Zm), 0>;
+}
+
+multiclass sme2_mla_add_sub_array_vg2_multi_D<string mnemonic, bits<2> op>{
+ def NAME : sme2_mla_add_sub_array_vg2_multi<0b1, op, MatrixOp64, ZZ_d_mul_r, mnemonic>;
+
+ def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
+ (!cast<Instruction>(NAME) MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZ_d_mul_r:$Zn, ZZ_d_mul_r:$Zm), 0>;
+}
+
+class sme2_mla_add_sub_array_vg4_multi_base<bit sz, bits<2> op,
+ MatrixOperand matrix_ty,
+ RegisterOperand multi_vector_ty,
+ string mnemonic>
+ : I<(outs matrix_ty:$ZAd),
+ (ins matrix_ty:$_ZAd, MatrixIndexGPR32Op8_11:$Rv,
+ sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, multi_vector_ty:$Zm),
+ mnemonic, "\t$ZAd[$Rv, $imm3, vgx4], $Zn, $Zm",
+ "", []>, Sched<[]>{
+ bits<3> Zm;
+ bits<3> Zn;
+ bits<2> Rv;
+ bits<3> imm3;
+ let Inst{31-23} = 0b110000011;
+ let Inst{22} = sz;
+ let Inst{21} = 0b1;
+ let Inst{20-18} = Zm;
+ let Inst{17-15} = 0b010;
+ let Inst{14-13} = Rv;
+ let Inst{12-10} = 0b110;
+ let Inst{9-7} = Zn;
+ let Inst{6-5} = 0b00;
+ let Inst{4-3} = op;
+ let Inst{2-0} = imm3;
+ let Constraints = "$ZAd = $_ZAd";
+}
+
+multiclass sme2_mla_add_sub_array_vg4_multi_S<string mnemonic, bits<2> op>{
+ def NAME : sme2_mla_add_sub_array_vg4_multi_base<0b0, op, MatrixOp32, ZZZZ_s_mul_r, mnemonic>;
+
+ def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
+ (!cast<Instruction>(NAME) MatrixOp32:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZZZ_s_mul_r:$Zn, ZZZZ_s_mul_r:$Zm), 0>;
+}
+
+multiclass sme2_mla_add_sub_array_vg4_multi_D<string mnemonic, bits<2> op>{
+ def NAME : sme2_mla_add_sub_array_vg4_multi_base<0b1, op, MatrixOp64, ZZZZ_d_mul_r, mnemonic>;
+
+ def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
+ (!cast<Instruction>(NAME) MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZZZ_d_mul_r:$Zn, ZZZZ_d_mul_r:$Zm), 0>;
+}
diff --git a/llvm/test/MC/AArch64/SME2/add-diagnostics.s b/llvm/test/MC/AArch64/SME2/add-diagnostics.s
index cd7c2f0c66167..f9029d0231c1d 100644
--- a/llvm/test/MC/AArch64/SME2/add-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2/add-diagnostics.s
@@ -13,6 +13,16 @@ add za.d[w8, -1, vgx4], {z0.s-z3.s}, z0.s
// CHECK-NEXT: add za.d[w8, -1, vgx4], {z0.s-z3.s}, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+add za.s[w8, 8], {z0.s - z1.s}, {z2.s - z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: add za.s[w8, 8], {z0.s - z1.s}, {z2.s - z3.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+add za.s[w8, -1], {z0.s - z3.s}, {z4.s - z7.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: add za.s[w8, -1], {z0.s - z3.s}, {z4.s - z7.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector select register
@@ -26,6 +36,12 @@ add za.s[w12, 0], {z0.s-z1.s}, z0.s
// CHECK-NEXT: add za.s[w12, 0], {z0.s-z1.s}, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+add za.s[w7, 0], {z0.s - z1.s}, {z2.s - z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: add za.s[w7, 0], {z0.s - z1.s}, {z2.s - z3.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:$
+
+
// --------------------------------------------------------------------------//
// Invalid Matrix Operand
@@ -47,3 +63,31 @@ add za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
// CHECK-NEXT: za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+add za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: add za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+add za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: add za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+add za.d[w11, 7, vgx4], {z12.d-z15.d}, {z9.d-z12.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: add za.d[w11, 7, vgx4], {z12.d-z15.d}, {z9.d-z12.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+add za.s[w10, 3], {z10.b-z11.b}, {z20.b-z21.b}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: add za.s[w10, 3], {z10.b-z11.b}, {z20.b-z21.b}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+add za.d[w11, 7], {z28.h - z31.h}, {z28.h - z31.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: add za.d[w11, 7], {z28.h - z31.h}, {z28.h - z31.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/add.s b/llvm/test/MC/AArch64/SME2/add.s
index d5c2d51c9b4cc..43e686248263d 100644
--- a/llvm/test/MC/AArch64/SME2/add.s
+++ b/llvm/test/MC/AArch64/SME2/add.s
@@ -157,6 +157,151 @@ add za.s[w9, 7], {z12.s - z13.s}, z11.s // 11000001-00101011-00111001-10010
// CHECK-UNKNOWN: c12b3997 <unknown>
+add za.s[w8, 0, vgx2], {z0.s, z1.s}, {z0.s, z1.s} // 11000001, 10100000, 00011000, 00010000
+// CHECK-INST: add za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x10,0x18,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01810 <unknown>
+
+add za.s[w8, 0], {z0.s - z1.s}, {z0.s - z1.s} // 11000001-10100000-00011000-00010000
+// CHECK-INST: add za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x10,0x18,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01810 <unknown>
+
+add za.s[w10, 5, vgx2], {z10.s, z11.s}, {z20.s, z21.s} // 11000001, 10110100, 01011001, 01010101
+// CHECK-INST: add za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x55,0x59,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b45955 <unknown>
+
+add za.s[w10, 5], {z10.s - z11.s}, {z20.s - z21.s} // 11000001-10110100-01011001-01010101
+// CHECK-INST: add za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x55,0x59,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b45955 <unknown>
+
+add za.s[w11, 7, vgx2], {z12.s, z13.s}, {z8.s, z9.s} // 11000001, 10101000, 01111001, 10010111
+// CHECK-INST: add za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x97,0x79,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a87997 <unknown>
+
+add za.s[w11, 7], {z12.s - z13.s}, {z8.s - z9.s} // 11000001-10101000-01111001-10010111
+// CHECK-INST: add za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x97,0x79,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a87997 <unknown>
+
+add za.s[w11, 7, vgx2], {z30.s, z31.s}, {z30.s, z31.s} // 11000001, 10111110, 01111011, 11010111
+// CHECK-INST: add za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xd7,0x7b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be7bd7 <unknown>
+
+add za.s[w11, 7], {z30.s - z31.s}, {z30.s - z31.s} // 11000001-10111110-01111011-11010111
+// CHECK-INST: add za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xd7,0x7b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be7bd7 <unknown>
+
+add za.s[w8, 5, vgx2], {z16.s, z17.s}, {z16.s, z17.s} // 11000001, 10110000, 00011010, 00010101
+// CHECK-INST: add za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }
+// CHECK-ENCODING: [0x15,0x1a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b01a15 <unknown>
+
+add za.s[w8, 5], {z16.s - z17.s}, {z16.s - z17.s} // 11000001-10110000-00011010-00010101
+// CHECK-INST: add za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }
+// CHECK-ENCODING: [0x15,0x1a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b01a15 <unknown>
+
+add za.s[w8, 1, vgx2], {z0.s, z1.s}, {z30.s, z31.s} // 11000001, 10111110, 00011000, 00010001
+// CHECK-INST: add za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x11,0x18,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1811 <unknown>
+
+add za.s[w8, 1], {z0.s - z1.s}, {z30.s - z31.s} // 11000001-10111110-00011000-00010001
+// CHECK-INST: add za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x11,0x18,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1811 <unknown>
+
+add za.s[w10, 0, vgx2], {z18.s, z19.s}, {z20.s, z21.s} // 11000001, 10110100, 01011010, 01010000
+// CHECK-INST: add za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x50,0x5a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b45a50 <unknown>
+
+add za.s[w10, 0], {z18.s - z19.s}, {z20.s - z21.s} // 11000001-10110100-01011010-01010000
+// CHECK-INST: add za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x50,0x5a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b45a50 <unknown>
+
+add za.s[w8, 0, vgx2], {z12.s, z13.s}, {z2.s, z3.s} // 11000001, 10100010, 00011001, 10010000
+// CHECK-INST: add za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }
+// CHECK-ENCODING: [0x90,0x19,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a21990 <unknown>
+
+add za.s[w8, 0], {z12.s - z13.s}, {z2.s - z3.s} // 11000001-10100010-00011001-10010000
+// CHECK-INST: add za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }
+// CHECK-ENCODING: [0x90,0x19,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a21990 <unknown>
+
+add za.s[w10, 1, vgx2], {z0.s, z1.s}, {z26.s, z27.s} // 11000001, 10111010, 01011000, 00010001
+// CHECK-INST: add za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }
+// CHECK-ENCODING: [0x11,0x58,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba5811 <unknown>
+
+add za.s[w10, 1], {z0.s - z1.s}, {z26.s - z27.s} // 11000001-10111010-01011000-00010001
+// CHECK-INST: add za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }
+// CHECK-ENCODING: [0x11,0x58,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba5811 <unknown>
+
+add za.s[w8, 5, vgx2], {z22.s, z23.s}, {z30.s, z31.s} // 11000001, 10111110, 00011010, 11010101
+// CHECK-INST: add za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xd5,0x1a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1ad5 <unknown>
+
+add za.s[w8, 5], {z22.s - z23.s}, {z30.s - z31.s} // 11000001-10111110-00011010-11010101
+// CHECK-INST: add za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xd5,0x1a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1ad5 <unknown>
+
+add za.s[w11, 2, vgx2], {z8.s, z9.s}, {z0.s, z1.s} // 11000001, 10100000, 01111001, 00010010
+// CHECK-INST: add za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x12,0x79,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07912 <unknown>
+
+add za.s[w11, 2], {z8.s - z9.s}, {z0.s - z1.s} // 11000001-10100000-01111001-00010010
+// CHECK-INST: add za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x12,0x79,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07912 <unknown>
+
+add za.s[w9, 7, vgx2], {z12.s, z13.s}, {z10.s, z11.s} // 11000001, 10101010, 00111001, 10010111
+// CHECK-INST: add za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x97,0x39,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa3997 <unknown>
+
+add za.s[w9, 7], {z12.s - z13.s}, {z10.s - z11.s} // 11000001-10101010-00111001-10010111
+// CHECK-INST: add za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x97,0x39,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa3997 <unknown>
+
+
add za.d[w8, 0, vgx2], {z0.d, z1.d}, z0.d // 11000001, 01100000, 00011000, 00010000
// CHECK-INST: add za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d
// CHECK-ENCODING: [0x10,0x18,0x60,0xc1]
@@ -302,6 +447,151 @@ add za.d[w9, 7], {z12.d - z13.d}, z11.d // 11000001-01101011-00111001-10010
// CHECK-UNKNOWN: c16b3997 <unknown>
+add za.d[w8, 0, vgx2], {z0.d, z1.d}, {z0.d, z1.d} // 11000001, 11100000, 00011000, 00010000
+// CHECK-INST: add za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x10,0x18,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01810 <unknown>
+
+add za.d[w8, 0], {z0.d - z1.d}, {z0.d - z1.d} // 11000001-11100000-00011000-00010000
+// CHECK-INST: add za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x10,0x18,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01810 <unknown>
+
+add za.d[w10, 5, vgx2], {z10.d, z11.d}, {z20.d, z21.d} // 11000001, 11110100, 01011001, 01010101
+// CHECK-INST: add za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x55,0x59,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f45955 <unknown>
+
+add za.d[w10, 5], {z10.d - z11.d}, {z20.d - z21.d} // 11000001-11110100-01011001-01010101
+// CHECK-INST: add za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x55,0x59,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f45955 <unknown>
+
+add za.d[w11, 7, vgx2], {z12.d, z13.d}, {z8.d, z9.d} // 11000001, 11101000, 01111001, 10010111
+// CHECK-INST: add za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x97,0x79,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e87997 <unknown>
+
+add za.d[w11, 7], {z12.d - z13.d}, {z8.d - z9.d} // 11000001-11101000-01111001-10010111
+// CHECK-INST: add za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x97,0x79,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e87997 <unknown>
+
+add za.d[w11, 7, vgx2], {z30.d, z31.d}, {z30.d, z31.d} // 11000001, 11111110, 01111011, 11010111
+// CHECK-INST: add za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xd7,0x7b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe7bd7 <unknown>
+
+add za.d[w11, 7], {z30.d - z31.d}, {z30.d - z31.d} // 11000001-11111110-01111011-11010111
+// CHECK-INST: add za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xd7,0x7b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe7bd7 <unknown>
+
+add za.d[w8, 5, vgx2], {z16.d, z17.d}, {z16.d, z17.d} // 11000001, 11110000, 00011010, 00010101
+// CHECK-INST: add za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }
+// CHECK-ENCODING: [0x15,0x1a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f01a15 <unknown>
+
+add za.d[w8, 5], {z16.d - z17.d}, {z16.d - z17.d} // 11000001-11110000-00011010-00010101
+// CHECK-INST: add za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }
+// CHECK-ENCODING: [0x15,0x1a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f01a15 <unknown>
+
+add za.d[w8, 1, vgx2], {z0.d, z1.d}, {z30.d, z31.d} // 11000001, 11111110, 00011000, 00010001
+// CHECK-INST: add za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x11,0x18,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1811 <unknown>
+
+add za.d[w8, 1], {z0.d - z1.d}, {z30.d - z31.d} // 11000001-11111110-00011000-00010001
+// CHECK-INST: add za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x11,0x18,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1811 <unknown>
+
+add za.d[w10, 0, vgx2], {z18.d, z19.d}, {z20.d, z21.d} // 11000001, 11110100, 01011010, 01010000
+// CHECK-INST: add za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x50,0x5a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f45a50 <unknown>
+
+add za.d[w10, 0], {z18.d - z19.d}, {z20.d - z21.d} // 11000001-11110100-01011010-01010000
+// CHECK-INST: add za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x50,0x5a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f45a50 <unknown>
+
+add za.d[w8, 0, vgx2], {z12.d, z13.d}, {z2.d, z3.d} // 11000001, 11100010, 00011001, 10010000
+// CHECK-INST: add za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }
+// CHECK-ENCODING: [0x90,0x19,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e21990 <unknown>
+
+add za.d[w8, 0], {z12.d - z13.d}, {z2.d - z3.d} // 11000001-11100010-00011001-10010000
+// CHECK-INST: add za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }
+// CHECK-ENCODING: [0x90,0x19,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e21990 <unknown>
+
+add za.d[w10, 1, vgx2], {z0.d, z1.d}, {z26.d, z27.d} // 11000001, 11111010, 01011000, 00010001
+// CHECK-INST: add za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }
+// CHECK-ENCODING: [0x11,0x58,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa5811 <unknown>
+
+add za.d[w10, 1], {z0.d - z1.d}, {z26.d - z27.d} // 11000001-11111010-01011000-00010001
+// CHECK-INST: add za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }
+// CHECK-ENCODING: [0x11,0x58,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa5811 <unknown>
+
+add za.d[w8, 5, vgx2], {z22.d, z23.d}, {z30.d, z31.d} // 11000001, 11111110, 00011010, 11010101
+// CHECK-INST: add za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xd5,0x1a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1ad5 <unknown>
+
+add za.d[w8, 5], {z22.d - z23.d}, {z30.d - z31.d} // 11000001-11111110-00011010-11010101
+// CHECK-INST: add za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xd5,0x1a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1ad5 <unknown>
+
+add za.d[w11, 2, vgx2], {z8.d, z9.d}, {z0.d, z1.d} // 11000001, 11100000, 01111001, 00010010
+// CHECK-INST: add za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x12,0x79,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07912 <unknown>
+
+add za.d[w11, 2], {z8.d - z9.d}, {z0.d - z1.d} // 11000001-11100000-01111001-00010010
+// CHECK-INST: add za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x12,0x79,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07912 <unknown>
+
+add za.d[w9, 7, vgx2], {z12.d, z13.d}, {z10.d, z11.d} // 11000001, 11101010, 00111001, 10010111
+// CHECK-INST: add za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }
+// CHECK-ENCODING: [0x97,0x39,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea3997 <unknown>
+
+add za.d[w9, 7], {z12.d - z13.d}, {z10.d - z11.d} // 11000001-11101010-00111001-10010111
+// CHECK-INST: add za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }
+// CHECK-ENCODING: [0x97,0x39,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea3997 <unknown>
+
+
add za.s[w8, 0, vgx4], {z0.s - z3.s}, z0.s // 11000001-00110000-00011000-00010000
// CHECK-INST: add za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
// CHECK-ENCODING: [0x10,0x18,0x30,0xc1]
@@ -447,6 +737,145 @@ add za.s[w9, 7], {z12.s - z15.s}, z11.s // 11000001-00111011-00111001-10010
// CHECK-UNKNOWN: c13b3997 <unknown>
+add za.s[w8, 0], {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100001-00011000-00010000
+// CHECK-INST: add za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x10,0x18,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11810 <unknown>
+
+add za.s[w10, 5, vgx4], {z8.s - z11.s}, {z20.s - z23.s} // 11000001-10110101-01011001-00010101
+// CHECK-INST: add za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x15,0x59,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b55915 <unknown>
+
+add za.s[w10, 5], {z8.s - z11.s}, {z20.s - z23.s} // 11000001-10110101-01011001-00010101
+// CHECK-INST: add za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x15,0x59,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b55915 <unknown>
+
+add za.s[w11, 7, vgx4], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-01111001-10010111
+// CHECK-INST: add za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x97,0x79,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a97997 <unknown>
+
+add za.s[w11, 7], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-01111001-10010111
+// CHECK-INST: add za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x97,0x79,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a97997 <unknown>
+
+add za.s[w11, 7, vgx4], {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111101-01111011-10010111
+// CHECK-INST: add za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x97,0x7b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd7b97 <unknown>
+
+add za.s[w11, 7], {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111101-01111011-10010111
+// CHECK-INST: add za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x97,0x7b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd7b97 <unknown>
+
+add za.s[w8, 5, vgx4], {z16.s - z19.s}, {z16.s - z19.s} // 11000001-10110001-00011010-00010101
+// CHECK-INST: add za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }
+// CHECK-ENCODING: [0x15,0x1a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b11a15 <unknown>
+
+add za.s[w8, 5], {z16.s - z19.s}, {z16.s - z19.s} // 11000001-10110001-00011010-00010101
+// CHECK-INST: add za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }
+// CHECK-ENCODING: [0x15,0x1a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b11a15 <unknown>
+
+add za.s[w8, 1, vgx4], {z0.s - z3.s}, {z28.s - z31.s} // 11000001-10111101-00011000-00010001
+// CHECK-INST: add za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x11,0x18,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1811 <unknown>
+
+add za.s[w8, 1], {z0.s - z3.s}, {z28.s - z31.s} // 11000001-10111101-00011000-00010001
+// CHECK-INST: add za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x11,0x18,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1811 <unknown>
+
+add za.s[w10, 0, vgx4], {z16.s - z19.s}, {z20.s - z23.s} // 11000001-10110101-01011010-00010000
+// CHECK-INST: add za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x10,0x5a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b55a10 <unknown>
+
+add za.s[w10, 0], {z16.s - z19.s}, {z20.s - z23.s} // 11000001-10110101-01011010-00010000
+// CHECK-INST: add za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x10,0x5a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b55a10 <unknown>
+
+add za.s[w8, 0, vgx4], {z12.s - z15.s}, {z0.s - z3.s} // 11000001-10100001-00011001-10010000
+// CHECK-INST: add za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x90,0x19,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11990 <unknown>
+
+add za.s[w8, 0], {z12.s - z15.s}, {z0.s - z3.s} // 11000001-10100001-00011001-10010000
+// CHECK-INST: add za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x90,0x19,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11990 <unknown>
+
+add za.s[w10, 1, vgx4], {z0.s - z3.s}, {z24.s - z27.s} // 11000001-10111001-01011000-00010001
+// CHECK-INST: add za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }
+// CHECK-ENCODING: [0x11,0x58,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b95811 <unknown>
+
+add za.s[w10, 1], {z0.s - z3.s}, {z24.s - z27.s} // 11000001-10111001-01011000-00010001
+// CHECK-INST: add za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }
+// CHECK-ENCODING: [0x11,0x58,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b95811 <unknown>
+
+add za.s[w8, 5, vgx4], {z20.s - z23.s}, {z28.s - z31.s} // 11000001-10111101-00011010-10010101
+// CHECK-INST: add za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x95,0x1a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1a95 <unknown>
+
+add za.s[w8, 5], {z20.s - z23.s}, {z28.s - z31.s} // 11000001-10111101-00011010-10010101
+// CHECK-INST: add za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x95,0x1a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1a95 <unknown>
+
+add za.s[w11, 2, vgx4], {z8.s - z11.s}, {z0.s - z3.s} // 11000001-10100001-01111001-00010010
+// CHECK-INST: add za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x12,0x79,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17912 <unknown>
+
+add za.s[w11, 2], {z8.s - z11.s}, {z0.s - z3.s} // 11000001-10100001-01111001-00010010
+// CHECK-INST: add za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x12,0x79,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17912 <unknown>
+
+add za.s[w9, 7, vgx4], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-00111001-10010111
+// CHECK-INST: add za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x97,0x39,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a93997 <unknown>
+
+add za.s[w9, 7], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-00111001-10010111
+// CHECK-INST: add za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x97,0x39,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a93997 <unknown>
+
+
add za.d[w8, 0, vgx4], {z0.d - z3.d}, z0.d // 11000001-01110000-00011000-00010000
// CHECK-INST: add za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d
// CHECK-ENCODING: [0x10,0x18,0x70,0xc1]
@@ -591,3 +1020,147 @@ add za.d[w9, 7], {z12.d - z15.d}, z11.d // 11000001-01111011-00111001-10010
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17b3997 <unknown>
+
+add za.d[w8, 0, vgx4], {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100001-00011000-00010000
+// CHECK-INST: add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x10,0x18,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11810 <unknown>
+
+add za.d[w8, 0], {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100001-00011000-00010000
+// CHECK-INST: add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x10,0x18,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11810 <unknown>
+
+add za.d[w10, 5, vgx4], {z8.d - z11.d}, {z20.d - z23.d} // 11000001-11110101-01011001-00010101
+// CHECK-INST: add za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x15,0x59,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55915 <unknown>
+
+add za.d[w10, 5], {z8.d - z11.d}, {z20.d - z23.d} // 11000001-11110101-01011001-00010101
+// CHECK-INST: add za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x15,0x59,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55915 <unknown>
+
+add za.d[w11, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-01111001-10010111
+// CHECK-INST: add za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x97,0x79,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e97997 <unknown>
+
+add za.d[w11, 7], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-01111001-10010111
+// CHECK-INST: add za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x97,0x79,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e97997 <unknown>
+
+add za.d[w11, 7, vgx4], {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111101-01111011-10010111
+// CHECK-INST: add za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x97,0x7b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd7b97 <unknown>
+
+add za.d[w11, 7], {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111101-01111011-10010111
+// CHECK-INST: add za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x97,0x7b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd7b97 <unknown>
+
+add za.d[w8, 5, vgx4], {z16.d - z19.d}, {z16.d - z19.d} // 11000001-11110001-00011010-00010101
+// CHECK-INST: add za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }
+// CHECK-ENCODING: [0x15,0x1a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f11a15 <unknown>
+
+add za.d[w8, 5], {z16.d - z19.d}, {z16.d - z19.d} // 11000001-11110001-00011010-00010101
+// CHECK-INST: add za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }
+// CHECK-ENCODING: [0x15,0x1a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f11a15 <unknown>
+
+add za.d[w8, 1, vgx4], {z0.d - z3.d}, {z28.d - z31.d} // 11000001-11111101-00011000-00010001
+// CHECK-INST: add za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x11,0x18,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1811 <unknown>
+
+add za.d[w8, 1], {z0.d - z3.d}, {z28.d - z31.d} // 11000001-11111101-00011000-00010001
+// CHECK-INST: add za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x11,0x18,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1811 <unknown>
+
+add za.d[w10, 0, vgx4], {z16.d - z19.d}, {z20.d - z23.d} // 11000001-11110101-01011010-00010000
+// CHECK-INST: add za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x10,0x5a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55a10 <unknown>
+
+add za.d[w10, 0], {z16.d - z19.d}, {z20.d - z23.d} // 11000001-11110101-01011010-00010000
+// CHECK-INST: add za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x10,0x5a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55a10 <unknown>
+
+add za.d[w8, 0, vgx4], {z12.d - z15.d}, {z0.d - z3.d} // 11000001-11100001-00011001-10010000
+// CHECK-INST: add za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x90,0x19,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11990 <unknown>
+
+add za.d[w8, 0], {z12.d - z15.d}, {z0.d - z3.d} // 11000001-11100001-00011001-10010000
+// CHECK-INST: add za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x90,0x19,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11990 <unknown>
+
+add za.d[w10, 1, vgx4], {z0.d - z3.d}, {z24.d - z27.d} // 11000001-11111001-01011000-00010001
+// CHECK-INST: add za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }
+// CHECK-ENCODING: [0x11,0x58,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f95811 <unknown>
+
+add za.d[w10, 1], {z0.d - z3.d}, {z24.d - z27.d} // 11000001-11111001-01011000-00010001
+// CHECK-INST: add za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }
+// CHECK-ENCODING: [0x11,0x58,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f95811 <unknown>
+
+add za.d[w8, 5, vgx4], {z20.d - z23.d}, {z28.d - z31.d} // 11000001-11111101-00011010-10010101
+// CHECK-INST: add za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x95,0x1a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1a95 <unknown>
+
+add za.d[w8, 5], {z20.d - z23.d}, {z28.d - z31.d} // 11000001-11111101-00011010-10010101
+// CHECK-INST: add za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x95,0x1a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1a95 <unknown>
+
+add za.d[w11, 2, vgx4], {z8.d - z11.d}, {z0.d - z3.d} // 11000001-11100001-01111001-00010010
+// CHECK-INST: add za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x12,0x79,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17912 <unknown>
+
+add za.d[w11, 2], {z8.d - z11.d}, {z0.d - z3.d} // 11000001-11100001-01111001-00010010
+// CHECK-INST: add za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x12,0x79,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17912 <unknown>
+
+add za.d[w9, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-00111001-10010111
+// CHECK-INST: add za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x97,0x39,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e93997 <unknown>
+
+add za.d[w9, 7], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-00111001-10010111
+// CHECK-INST: add za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x97,0x39,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e93997 <unknown>
diff --git a/llvm/test/MC/AArch64/SME2/fmla-diagnostics.s b/llvm/test/MC/AArch64/SME2/fmla-diagnostics.s
index 83db84e54a1b2..8d4d82f9a34a3 100644
--- a/llvm/test/MC/AArch64/SME2/fmla-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2/fmla-diagnostics.s
@@ -13,6 +13,16 @@ fmla za.d[w8, -1, vgx4], {z0.s-z3.s}, z0.s
// CHECK-NEXT: fmla za.d[w8, -1, vgx4], {z0.s-z3.s}, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+fmla za.s[w8, 8], {z0.s - z1.s}, {z2.s - z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: fmla za.s[w8, 8], {z0.s - z1.s}, {z2.s - z3.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmla za.s[w8, -1], {z0.s - z3.s}, {z4.s - z7.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: fmla za.s[w8, -1], {z0.s - z3.s}, {z4.s - z7.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector select register
@@ -26,6 +36,11 @@ fmla za.s[w12, 0], {z0.s-z1.s}, z0.s
// CHECK-NEXT: fmla za.s[w12, 0], {z0.s-z1.s}, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+fmla za.s[w7, 0], {z0.s - z1.s}, {z2.s - z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: fmla za.s[w7, 0], {z0.s - z1.s}, {z2.s - z3.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:$
+
// --------------------------------------------------------------------------//
// Invalid Matrix Operand
@@ -34,7 +49,6 @@ fmla za.h[w8, #0], {z0.h-z3.h}, z4.h
// CHECK-NEXT: fmla za.h[w8, #0], {z0.h-z3.h}, z4.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
// --------------------------------------------------------------------------//
// Invalid vector grouping
@@ -48,3 +62,30 @@ fmla za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
// CHECK-NEXT: za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+fmla za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: fmla za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmla za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: fmla za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmla za.d[w11, 7, vgx4], {z12.d-z15.d}, {z9.d-z12.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: fmla za.d[w11, 7, vgx4], {z12.d-z15.d}, {z9.d-z12.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmla za.s[w10, 3], {z10.b-z11.b}, {z20.b-z21.b}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmla za.s[w10, 3], {z10.b-z11.b}, {z20.b-z21.b}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmla za.d[w11, 7], {z28.h - z31.h}, {z28.h - z31.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmla za.d[w11, 7], {z28.h - z31.h}, {z28.h - z31.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/fmla.s b/llvm/test/MC/AArch64/SME2/fmla.s
index 92d433ef8d161..1f46ad3a70b53 100644
--- a/llvm/test/MC/AArch64/SME2/fmla.s
+++ b/llvm/test/MC/AArch64/SME2/fmla.s
@@ -157,6 +157,151 @@ fmla za.d[w9, 7], {z12.d - z13.d}, z11.d // 11000001-01101011-00111001-10000
// CHECK-UNKNOWN: c16b3987 <unknown>
+fmla za.d[w8, 0, vgx2], {z0.d, z1.d}, {z0.d, z1.d} // 11000001, 11100000, 00011000, 00000000
+// CHECK-INST: fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x00,0x18,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01800 <unknown>
+
+fmla za.d[w8, 0], {z0.d - z1.d}, {z0.d - z1.d} // 11000001-11100000-00011000-00000000
+// CHECK-INST: fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x00,0x18,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01800 <unknown>
+
+fmla za.d[w10, 5, vgx2], {z10.d, z11.d}, {z20.d, z21.d} // 11000001, 11110100, 01011001, 01000101
+// CHECK-INST: fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x45,0x59,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f45945 <unknown>
+
+fmla za.d[w10, 5], {z10.d - z11.d}, {z20.d - z21.d} // 11000001-11110100-01011001-01000101
+// CHECK-INST: fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x45,0x59,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f45945 <unknown>
+
+fmla za.d[w11, 7, vgx2], {z12.d, z13.d}, {z8.d, z9.d} // 11000001, 11101000, 01111001, 10000111
+// CHECK-INST: fmla za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x87,0x79,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e87987 <unknown>
+
+fmla za.d[w11, 7], {z12.d - z13.d}, {z8.d - z9.d} // 11000001-11101000-01111001-10000111
+// CHECK-INST: fmla za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x87,0x79,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e87987 <unknown>
+
+fmla za.d[w11, 7, vgx2], {z30.d, z31.d}, {z30.d, z31.d} // 11000001, 11111110, 01111011, 11000111
+// CHECK-INST: fmla za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xc7,0x7b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe7bc7 <unknown>
+
+fmla za.d[w11, 7], {z30.d - z31.d}, {z30.d - z31.d} // 11000001-11111110-01111011-11000111
+// CHECK-INST: fmla za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xc7,0x7b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe7bc7 <unknown>
+
+fmla za.d[w8, 5, vgx2], {z16.d, z17.d}, {z16.d, z17.d} // 11000001, 11110000, 00011010, 00000101
+// CHECK-INST: fmla za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }
+// CHECK-ENCODING: [0x05,0x1a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f01a05 <unknown>
+
+fmla za.d[w8, 5], {z16.d - z17.d}, {z16.d - z17.d} // 11000001-11110000-00011010-00000101
+// CHECK-INST: fmla za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }
+// CHECK-ENCODING: [0x05,0x1a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f01a05 <unknown>
+
+fmla za.d[w8, 1, vgx2], {z0.d, z1.d}, {z30.d, z31.d} // 11000001, 11111110, 00011000, 00000001
+// CHECK-INST: fmla za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x01,0x18,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1801 <unknown>
+
+fmla za.d[w8, 1], {z0.d - z1.d}, {z30.d - z31.d} // 11000001-11111110-00011000-00000001
+// CHECK-INST: fmla za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x01,0x18,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1801 <unknown>
+
+fmla za.d[w10, 0, vgx2], {z18.d, z19.d}, {z20.d, z21.d} // 11000001, 11110100, 01011010, 01000000
+// CHECK-INST: fmla za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x40,0x5a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f45a40 <unknown>
+
+fmla za.d[w10, 0], {z18.d - z19.d}, {z20.d - z21.d} // 11000001-11110100-01011010-01000000
+// CHECK-INST: fmla za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x40,0x5a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f45a40 <unknown>
+
+fmla za.d[w8, 0, vgx2], {z12.d, z13.d}, {z2.d, z3.d} // 11000001, 11100010, 00011001, 10000000
+// CHECK-INST: fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }
+// CHECK-ENCODING: [0x80,0x19,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e21980 <unknown>
+
+fmla za.d[w8, 0], {z12.d - z13.d}, {z2.d - z3.d} // 11000001-11100010-00011001-10000000
+// CHECK-INST: fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }
+// CHECK-ENCODING: [0x80,0x19,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e21980 <unknown>
+
+fmla za.d[w10, 1, vgx2], {z0.d, z1.d}, {z26.d, z27.d} // 11000001, 11111010, 01011000, 00000001
+// CHECK-INST: fmla za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }
+// CHECK-ENCODING: [0x01,0x58,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa5801 <unknown>
+
+fmla za.d[w10, 1], {z0.d - z1.d}, {z26.d - z27.d} // 11000001-11111010-01011000-00000001
+// CHECK-INST: fmla za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }
+// CHECK-ENCODING: [0x01,0x58,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa5801 <unknown>
+
+fmla za.d[w8, 5, vgx2], {z22.d, z23.d}, {z30.d, z31.d} // 11000001, 11111110, 00011010, 11000101
+// CHECK-INST: fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xc5,0x1a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1ac5 <unknown>
+
+fmla za.d[w8, 5], {z22.d - z23.d}, {z30.d - z31.d} // 11000001-11111110-00011010-11000101
+// CHECK-INST: fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xc5,0x1a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1ac5 <unknown>
+
+fmla za.d[w11, 2, vgx2], {z8.d, z9.d}, {z0.d, z1.d} // 11000001, 11100000, 01111001, 00000010
+// CHECK-INST: fmla za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x02,0x79,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07902 <unknown>
+
+fmla za.d[w11, 2], {z8.d - z9.d}, {z0.d - z1.d} // 11000001-11100000-01111001-00000010
+// CHECK-INST: fmla za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x02,0x79,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e07902 <unknown>
+
+fmla za.d[w9, 7, vgx2], {z12.d, z13.d}, {z10.d, z11.d} // 11000001, 11101010, 00111001, 10000111
+// CHECK-INST: fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }
+// CHECK-ENCODING: [0x87,0x39,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea3987 <unknown>
+
+fmla za.d[w9, 7], {z12.d - z13.d}, {z10.d - z11.d} // 11000001-11101010-00111001-10000111
+// CHECK-INST: fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }
+// CHECK-ENCODING: [0x87,0x39,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea3987 <unknown>
+
+
fmla za.s[w8, 0, vgx2], {z0.s, z1.s}, z0.s // 11000001, 00100000, 00011000, 00000000
// CHECK-INST: fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s
// CHECK-ENCODING: [0x00,0x18,0x20,0xc1]
@@ -302,6 +447,151 @@ fmla za.s[w9, 7], {z12.s - z13.s}, z11.s // 11000001-00101011-00111001-10000
// CHECK-UNKNOWN: c12b3987 <unknown>
+fmla za.s[w8, 0, vgx2], {z0.s, z1.s}, {z0.s, z1.s} // 11000001, 10100000, 00011000, 00000000
+// CHECK-INST: fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0x18,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01800 <unknown>
+
+fmla za.s[w8, 0], {z0.s - z1.s}, {z0.s - z1.s} // 11000001-10100000-00011000-00000000
+// CHECK-INST: fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0x18,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01800 <unknown>
+
+fmla za.s[w10, 5, vgx2], {z10.s, z11.s}, {z20.s, z21.s} // 11000001, 10110100, 01011001, 01000101
+// CHECK-INST: fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x45,0x59,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b45945 <unknown>
+
+fmla za.s[w10, 5], {z10.s - z11.s}, {z20.s - z21.s} // 11000001-10110100-01011001-01000101
+// CHECK-INST: fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x45,0x59,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b45945 <unknown>
+
+fmla za.s[w11, 7, vgx2], {z12.s, z13.s}, {z8.s, z9.s} // 11000001, 10101000, 01111001, 10000111
+// CHECK-INST: fmla za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x87,0x79,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a87987 <unknown>
+
+fmla za.s[w11, 7], {z12.s - z13.s}, {z8.s - z9.s} // 11000001-10101000-01111001-10000111
+// CHECK-INST: fmla za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x87,0x79,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a87987 <unknown>
+
+fmla za.s[w11, 7, vgx2], {z30.s, z31.s}, {z30.s, z31.s} // 11000001, 10111110, 01111011, 11000111
+// CHECK-INST: fmla za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xc7,0x7b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be7bc7 <unknown>
+
+fmla za.s[w11, 7], {z30.s - z31.s}, {z30.s - z31.s} // 11000001-10111110-01111011-11000111
+// CHECK-INST: fmla za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xc7,0x7b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be7bc7 <unknown>
+
+fmla za.s[w8, 5, vgx2], {z16.s, z17.s}, {z16.s, z17.s} // 11000001, 10110000, 00011010, 00000101
+// CHECK-INST: fmla za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }
+// CHECK-ENCODING: [0x05,0x1a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b01a05 <unknown>
+
+fmla za.s[w8, 5], {z16.s - z17.s}, {z16.s - z17.s} // 11000001-10110000-00011010-00000101
+// CHECK-INST: fmla za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }
+// CHECK-ENCODING: [0x05,0x1a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b01a05 <unknown>
+
+fmla za.s[w8, 1, vgx2], {z0.s, z1.s}, {z30.s, z31.s} // 11000001, 10111110, 00011000, 00000001
+// CHECK-INST: fmla za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x01,0x18,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1801 <unknown>
+
+fmla za.s[w8, 1], {z0.s - z1.s}, {z30.s - z31.s} // 11000001-10111110-00011000-00000001
+// CHECK-INST: fmla za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x01,0x18,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1801 <unknown>
+
+fmla za.s[w10, 0, vgx2], {z18.s, z19.s}, {z20.s, z21.s} // 11000001, 10110100, 01011010, 01000000
+// CHECK-INST: fmla za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x40,0x5a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b45a40 <unknown>
+
+fmla za.s[w10, 0], {z18.s - z19.s}, {z20.s - z21.s} // 11000001-10110100-01011010-01000000
+// CHECK-INST: fmla za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x40,0x5a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b45a40 <unknown>
+
+fmla za.s[w8, 0, vgx2], {z12.s, z13.s}, {z2.s, z3.s} // 11000001, 10100010, 00011001, 10000000
+// CHECK-INST: fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }
+// CHECK-ENCODING: [0x80,0x19,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a21980 <unknown>
+
+fmla za.s[w8, 0], {z12.s - z13.s}, {z2.s - z3.s} // 11000001-10100010-00011001-10000000
+// CHECK-INST: fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }
+// CHECK-ENCODING: [0x80,0x19,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a21980 <unknown>
+
+fmla za.s[w10, 1, vgx2], {z0.s, z1.s}, {z26.s, z27.s} // 11000001, 10111010, 01011000, 00000001
+// CHECK-INST: fmla za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }
+// CHECK-ENCODING: [0x01,0x58,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba5801 <unknown>
+
+fmla za.s[w10, 1], {z0.s - z1.s}, {z26.s - z27.s} // 11000001-10111010-01011000-00000001
+// CHECK-INST: fmla za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }
+// CHECK-ENCODING: [0x01,0x58,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba5801 <unknown>
+
+fmla za.s[w8, 5, vgx2], {z22.s, z23.s}, {z30.s, z31.s} // 11000001, 10111110, 00011010, 11000101
+// CHECK-INST: fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xc5,0x1a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1ac5 <unknown>
+
+fmla za.s[w8, 5], {z22.s - z23.s}, {z30.s - z31.s} // 11000001-10111110-00011010-11000101
+// CHECK-INST: fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xc5,0x1a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1ac5 <unknown>
+
+fmla za.s[w11, 2, vgx2], {z8.s, z9.s}, {z0.s, z1.s} // 11000001, 10100000, 01111001, 00000010
+// CHECK-INST: fmla za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x02,0x79,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07902 <unknown>
+
+fmla za.s[w11, 2], {z8.s - z9.s}, {z0.s - z1.s} // 11000001-10100000-01111001-00000010
+// CHECK-INST: fmla za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x02,0x79,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a07902 <unknown>
+
+fmla za.s[w9, 7, vgx2], {z12.s, z13.s}, {z10.s, z11.s} // 11000001, 10101010, 00111001, 10000111
+// CHECK-INST: fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x87,0x39,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa3987 <unknown>
+
+fmla za.s[w9, 7], {z12.s - z13.s}, {z10.s - z11.s} // 11000001-10101010-00111001-10000111
+// CHECK-INST: fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x87,0x39,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa3987 <unknown>
+
+
fmla za.d[w8, 0, vgx4], {z0.d - z3.d}, z0.d // 11000001-01110000-00011000-00000000
// CHECK-INST: fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d
// CHECK-ENCODING: [0x00,0x18,0x70,0xc1]
@@ -447,6 +737,151 @@ fmla za.d[w9, 7], {z12.d - z15.d}, z11.d // 11000001-01111011-00111001-10000
// CHECK-UNKNOWN: c17b3987 <unknown>
+fmla za.d[w8, 0, vgx4], {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100001-00011000-00000000
+// CHECK-INST: fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x00,0x18,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11800 <unknown>
+
+fmla za.d[w8, 0], {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100001-00011000-00000000
+// CHECK-INST: fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x00,0x18,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11800 <unknown>
+
+fmla za.d[w10, 5, vgx4], {z8.d - z11.d}, {z20.d - z23.d} // 11000001-11110101-01011001-00000101
+// CHECK-INST: fmla za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x05,0x59,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55905 <unknown>
+
+fmla za.d[w10, 5], {z8.d - z11.d}, {z20.d - z23.d} // 11000001-11110101-01011001-00000101
+// CHECK-INST: fmla za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x05,0x59,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55905 <unknown>
+
+fmla za.d[w11, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-01111001-10000111
+// CHECK-INST: fmla za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x87,0x79,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e97987 <unknown>
+
+fmla za.d[w11, 7], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-01111001-10000111
+// CHECK-INST: fmla za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x87,0x79,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e97987 <unknown>
+
+fmla za.d[w11, 7, vgx4], {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111101-01111011-10000111
+// CHECK-INST: fmla za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x87,0x7b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd7b87 <unknown>
+
+fmla za.d[w11, 7], {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111101-01111011-10000111
+// CHECK-INST: fmla za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x87,0x7b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd7b87 <unknown>
+
+fmla za.d[w8, 5, vgx4], {z16.d - z19.d}, {z16.d - z19.d} // 11000001-11110001-00011010-00000101
+// CHECK-INST: fmla za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }
+// CHECK-ENCODING: [0x05,0x1a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f11a05 <unknown>
+
+fmla za.d[w8, 5], {z16.d - z19.d}, {z16.d - z19.d} // 11000001-11110001-00011010-00000101
+// CHECK-INST: fmla za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }
+// CHECK-ENCODING: [0x05,0x1a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f11a05 <unknown>
+
+fmla za.d[w8, 1, vgx4], {z0.d - z3.d}, {z28.d - z31.d} // 11000001-11111101-00011000-00000001
+// CHECK-INST: fmla za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x01,0x18,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1801 <unknown>
+
+fmla za.d[w8, 1], {z0.d - z3.d}, {z28.d - z31.d} // 11000001-11111101-00011000-00000001
+// CHECK-INST: fmla za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x01,0x18,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1801 <unknown>
+
+fmla za.d[w10, 0, vgx4], {z16.d - z19.d}, {z20.d - z23.d} // 11000001-11110101-01011010-00000000
+// CHECK-INST: fmla za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x00,0x5a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55a00 <unknown>
+
+fmla za.d[w10, 0], {z16.d - z19.d}, {z20.d - z23.d} // 11000001-11110101-01011010-00000000
+// CHECK-INST: fmla za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x00,0x5a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55a00 <unknown>
+
+fmla za.d[w8, 0, vgx4], {z12.d - z15.d}, {z0.d - z3.d} // 11000001-11100001-00011001-10000000
+// CHECK-INST: fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x80,0x19,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11980 <unknown>
+
+fmla za.d[w8, 0], {z12.d - z15.d}, {z0.d - z3.d} // 11000001-11100001-00011001-10000000
+// CHECK-INST: fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x80,0x19,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11980 <unknown>
+
+fmla za.d[w10, 1, vgx4], {z0.d - z3.d}, {z24.d - z27.d} // 11000001-11111001-01011000-00000001
+// CHECK-INST: fmla za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }
+// CHECK-ENCODING: [0x01,0x58,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f95801 <unknown>
+
+fmla za.d[w10, 1], {z0.d - z3.d}, {z24.d - z27.d} // 11000001-11111001-01011000-00000001
+// CHECK-INST: fmla za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }
+// CHECK-ENCODING: [0x01,0x58,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f95801 <unknown>
+
+fmla za.d[w8, 5, vgx4], {z20.d - z23.d}, {z28.d - z31.d} // 11000001-11111101-00011010-10000101
+// CHECK-INST: fmla za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x85,0x1a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1a85 <unknown>
+
+fmla za.d[w8, 5], {z20.d - z23.d}, {z28.d - z31.d} // 11000001-11111101-00011010-10000101
+// CHECK-INST: fmla za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x85,0x1a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1a85 <unknown>
+
+fmla za.d[w11, 2, vgx4], {z8.d - z11.d}, {z0.d - z3.d} // 11000001-11100001-01111001-00000010
+// CHECK-INST: fmla za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x02,0x79,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17902 <unknown>
+
+fmla za.d[w11, 2], {z8.d - z11.d}, {z0.d - z3.d} // 11000001-11100001-01111001-00000010
+// CHECK-INST: fmla za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x02,0x79,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17902 <unknown>
+
+fmla za.d[w9, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-00111001-10000111
+// CHECK-INST: fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x87,0x39,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e93987 <unknown>
+
+fmla za.d[w9, 7], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-00111001-10000111
+// CHECK-INST: fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x87,0x39,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e93987 <unknown>
+
+
fmla za.s[w8, 0, vgx4], {z0.s - z3.s}, z0.s // 11000001-00110000-00011000-00000000
// CHECK-INST: fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
// CHECK-ENCODING: [0x00,0x18,0x30,0xc1]
@@ -591,3 +1026,149 @@ fmla za.s[w9, 7], {z12.s - z15.s}, z11.s // 11000001-00111011-00111001-10000
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13b3987 <unknown>
+
+
+fmla za.s[w8, 0, vgx4], {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100001-00011000-00000000
+// CHECK-INST: fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0x18,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11800 <unknown>
+
+fmla za.s[w8, 0], {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100001-00011000-00000000
+// CHECK-INST: fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0x18,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11800 <unknown>
+
+fmla za.s[w10, 5, vgx4], {z8.s - z11.s}, {z20.s - z23.s} // 11000001-10110101-01011001-00000101
+// CHECK-INST: fmla za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x05,0x59,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b55905 <unknown>
+
+fmla za.s[w10, 5], {z8.s - z11.s}, {z20.s - z23.s} // 11000001-10110101-01011001-00000101
+// CHECK-INST: fmla za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x05,0x59,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b55905 <unknown>
+
+fmla za.s[w11, 7, vgx4], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-01111001-10000111
+// CHECK-INST: fmla za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x87,0x79,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a97987 <unknown>
+
+fmla za.s[w11, 7], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-01111001-10000111
+// CHECK-INST: fmla za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x87,0x79,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a97987 <unknown>
+
+fmla za.s[w11, 7, vgx4], {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111101-01111011-10000111
+// CHECK-INST: fmla za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x87,0x7b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd7b87 <unknown>
+
+fmla za.s[w11, 7], {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111101-01111011-10000111
+// CHECK-INST: fmla za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x87,0x7b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd7b87 <unknown>
+
+fmla za.s[w8, 5, vgx4], {z16.s - z19.s}, {z16.s - z19.s} // 11000001-10110001-00011010-00000101
+// CHECK-INST: fmla za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }
+// CHECK-ENCODING: [0x05,0x1a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b11a05 <unknown>
+
+fmla za.s[w8, 5], {z16.s - z19.s}, {z16.s - z19.s} // 11000001-10110001-00011010-00000101
+// CHECK-INST: fmla za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }
+// CHECK-ENCODING: [0x05,0x1a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b11a05 <unknown>
+
+fmla za.s[w8, 1, vgx4], {z0.s - z3.s}, {z28.s - z31.s} // 11000001-10111101-00011000-00000001
+// CHECK-INST: fmla za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x01,0x18,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1801 <unknown>
+
+fmla za.s[w8, 1], {z0.s - z3.s}, {z28.s - z31.s} // 11000001-10111101-00011000-00000001
+// CHECK-INST: fmla za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x01,0x18,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1801 <unknown>
+
+fmla za.s[w10, 0, vgx4], {z16.s - z19.s}, {z20.s - z23.s} // 11000001-10110101-01011010-00000000
+// CHECK-INST: fmla za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x00,0x5a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b55a00 <unknown>
+
+fmla za.s[w10, 0], {z16.s - z19.s}, {z20.s - z23.s} // 11000001-10110101-01011010-00000000
+// CHECK-INST: fmla za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x00,0x5a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b55a00 <unknown>
+
+fmla za.s[w8, 0, vgx4], {z12.s - z15.s}, {z0.s - z3.s} // 11000001-10100001-00011001-10000000
+// CHECK-INST: fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x80,0x19,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11980 <unknown>
+
+fmla za.s[w8, 0], {z12.s - z15.s}, {z0.s - z3.s} // 11000001-10100001-00011001-10000000
+// CHECK-INST: fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x80,0x19,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11980 <unknown>
+
+fmla za.s[w10, 1, vgx4], {z0.s - z3.s}, {z24.s - z27.s} // 11000001-10111001-01011000-00000001
+// CHECK-INST: fmla za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }
+// CHECK-ENCODING: [0x01,0x58,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b95801 <unknown>
+
+fmla za.s[w10, 1], {z0.s - z3.s}, {z24.s - z27.s} // 11000001-10111001-01011000-00000001
+// CHECK-INST: fmla za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }
+// CHECK-ENCODING: [0x01,0x58,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b95801 <unknown>
+
+fmla za.s[w8, 5, vgx4], {z20.s - z23.s}, {z28.s - z31.s} // 11000001-10111101-00011010-10000101
+// CHECK-INST: fmla za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x85,0x1a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1a85 <unknown>
+
+fmla za.s[w8, 5], {z20.s - z23.s}, {z28.s - z31.s} // 11000001-10111101-00011010-10000101
+// CHECK-INST: fmla za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x85,0x1a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1a85 <unknown>
+
+fmla za.s[w11, 2, vgx4], {z8.s - z11.s}, {z0.s - z3.s} // 11000001-10100001-01111001-00000010
+// CHECK-INST: fmla za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x02,0x79,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17902 <unknown>
+
+fmla za.s[w11, 2], {z8.s - z11.s}, {z0.s - z3.s} // 11000001-10100001-01111001-00000010
+// CHECK-INST: fmla za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x02,0x79,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a17902 <unknown>
+
+fmla za.s[w9, 7, vgx4], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-00111001-10000111
+// CHECK-INST: fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x87,0x39,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a93987 <unknown>
+
+fmla za.s[w9, 7], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-00111001-10000111
+// CHECK-INST: fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x87,0x39,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a93987 <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/fmls-diagnostics.s b/llvm/test/MC/AArch64/SME2/fmls-diagnostics.s
index 9e762498ce0c1..3a751a6e5f033 100644
--- a/llvm/test/MC/AArch64/SME2/fmls-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2/fmls-diagnostics.s
@@ -48,3 +48,30 @@ fmls za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
// CHECK-NEXT: za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+fmls za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: fmls za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmls za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: fmls za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmls za.d[w11, 7, vgx4], {z12.d-z15.d}, {z9.d-z12.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: fmls za.d[w11, 7, vgx4], {z12.d-z15.d}, {z9.d-z12.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmls za.s[w10, 3], {z10.b-z11.b}, {z20.b-z21.b}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmls za.s[w10, 3], {z10.b-z11.b}, {z20.b-z21.b}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmls za.d[w11, 7], {z28.h - z31.h}, {z28.h - z31.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmls za.d[w11, 7], {z28.h - z31.h}, {z28.h - z31.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/fmls.s b/llvm/test/MC/AArch64/SME2/fmls.s
index b3d1f188fdd56..be9874c36c9e8 100644
--- a/llvm/test/MC/AArch64/SME2/fmls.s
+++ b/llvm/test/MC/AArch64/SME2/fmls.s
@@ -157,6 +157,163 @@ fmls za.d[w9, 7], {z12.d - z13.d}, z11.d // 11000001-01101011-00111001-10001
// CHECK-UNKNOWN: c16b398f <unknown>
+fmls za.d[w8, 0, vgx2], {z0.d, z1.d}, {z0.d, z1.d} // 11000001, 11100000, 00011000, 00001000
+// CHECK-INST: fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x08,0x18,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01808 <unknown>
+
+fmls za.d[w8, 0], {z0.d - z1.d}, {z0.d - z1.d} // 11000001-11100000-00011000-00001000
+// CHECK-INST: fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x08,0x18,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01808 <unknown>
+
+fmls za.d[w10, 5, vgx2], {z10.d, z11.d}, {z20.d, z21.d} // 11000001, 11110100, 01011001, 01001101
+// CHECK-INST: fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x4d,0x59,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4594d <unknown>
+
+fmls za.d[w10, 5], {z10.d - z11.d}, {z20.d - z21.d} // 11000001-11110100-01011001-01001101
+// CHECK-INST: fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x4d,0x59,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4594d <unknown>
+
+fmls za.d[w11, 7, vgx2], {z12.d, z13.d}, {z8.d, z9.d} // 11000001, 11101000, 01111001, 10001111
+// CHECK-INST: fmls za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x8f,0x79,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8798f <unknown>
+
+fmls za.d[w11, 7], {z12.d - z13.d}, {z8.d - z9.d} // 11000001-11101000-01111001-10001111
+// CHECK-INST: fmls za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x8f,0x79,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8798f <unknown>
+
+fmls za.d[w11, 7, vgx2], {z30.d, z31.d}, {z30.d, z31.d} // 11000001, 11111110, 01111011, 11001111
+// CHECK-INST: fmls za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xcf,0x7b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe7bcf <unknown>
+
+fmls za.d[w11, 7], {z30.d - z31.d}, {z30.d - z31.d} // 11000001-11111110-01111011-11001111
+// CHECK-INST: fmls za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xcf,0x7b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe7bcf <unknown>
+
+fmls za.d[w8, 5, vgx2], {z16.d, z17.d}, {z16.d, z17.d} // 11000001, 11110000, 00011010, 00001101
+// CHECK-INST: fmls za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }
+// CHECK-ENCODING: [0x0d,0x1a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f01a0d <unknown>
+
+fmls za.d[w8, 5], {z16.d - z17.d}, {z16.d - z17.d} // 11000001-11110000-00011010-00001101
+// CHECK-INST: fmls za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }
+// CHECK-ENCODING: [0x0d,0x1a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f01a0d <unknown>
+
+fmls za.d[w8, 1, vgx2], {z0.d, z1.d}, {z30.d, z31.d} // 11000001, 11111110, 00011000, 00001001
+// CHECK-INST: fmls za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x09,0x18,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1809 <unknown>
+
+fmls za.d[w8, 1], {z0.d - z1.d}, {z30.d - z31.d} // 11000001-11111110-00011000-00001001
+// CHECK-INST: fmls za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x09,0x18,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1809 <unknown>
+
+fmls za.d[w10, 0, vgx2], {z18.d, z19.d}, {z20.d, z21.d} // 11000001, 11110100, 01011010, 01001000
+// CHECK-INST: fmls za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x48,0x5a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f45a48 <unknown>
+
+fmls za.d[w10, 0], {z18.d - z19.d}, {z20.d - z21.d} // 11000001-11110100-01011010-01001000
+// CHECK-INST: fmls za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x48,0x5a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f45a48 <unknown>
+
+fmls za.d[w8, 0, vgx2], {z12.d, z13.d}, {z2.d, z3.d} // 11000001, 11100010, 00011001, 10001000
+// CHECK-INST: fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }
+// CHECK-ENCODING: [0x88,0x19,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e21988 <unknown>
+
+fmls za.d[w8, 0], {z12.d - z13.d}, {z2.d - z3.d} // 11000001-11100010-00011001-10001000
+// CHECK-INST: fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }
+// CHECK-ENCODING: [0x88,0x19,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e21988 <unknown>
+
+fmls za.d[w10, 1, vgx2], {z0.d, z1.d}, {z26.d, z27.d} // 11000001, 11111010, 01011000, 00001001
+// CHECK-INST: fmls za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }
+// CHECK-ENCODING: [0x09,0x58,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa5809 <unknown>
+
+fmls za.d[w10, 1], {z0.d - z1.d}, {z26.d - z27.d} // 11000001-11111010-01011000-00001001
+// CHECK-INST: fmls za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }
+// CHECK-ENCODING: [0x09,0x58,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa5809 <unknown>
+
+fmls za.d[w8, 5, vgx2], {z22.d, z23.d}, {z30.d, z31.d} // 11000001, 11111110, 00011010, 11001101
+// CHECK-INST: fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xcd,0x1a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1acd <unknown>
+
+fmls za.d[w8, 5], {z22.d - z23.d}, {z30.d - z31.d} // 11000001-11111110-00011010-11001101
+// CHECK-INST: fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xcd,0x1a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1acd <unknown>
+
+fmls za.d[w11, 2, vgx2], {z8.d, z9.d}, {z0.d, z1.d} // 11000001, 11100000, 01111001, 00001010
+// CHECK-INST: fmls za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x0a,0x79,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0790a <unknown>
+
+fmls za.d[w11, 2], {z8.d - z9.d}, {z0.d - z1.d} // 11000001-11100000-01111001-00001010
+// CHECK-INST: fmls za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x0a,0x79,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0790a <unknown>
+
+fmls za.d[w9, 7, vgx2], {z12.d, z13.d}, {z10.d, z11.d} // 11000001, 11101010, 00111001, 10001111
+// CHECK-INST: fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }
+// CHECK-ENCODING: [0x8f,0x39,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea398f <unknown>
+
+fmls za.d[w9, 7], {z12.d - z13.d}, {z10.d - z11.d} // 11000001-11101010-00111001-10001111
+// CHECK-INST: fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }
+// CHECK-ENCODING: [0x8f,0x39,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea398f <unknown>
+
+
+fmls za.s[w8, 0, vgx2], {z0.s, z1.s}, z0.s // 11000001, 00100000, 00011000, 00001000
+// CHECK-INST: fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x08,0x18,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1201808 <unknown>
+
+fmls za.s[w8, 0], {z0.s - z1.s}, z0.s // 11000001-00100000-00011000-00001000
+// CHECK-INST: fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x08,0x18,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1201808 <unknown>
+
fmls za.s[w10, 5, vgx2], {z10.s, z11.s}, z5.s // 11000001, 00100101, 01011001, 01001101
// CHECK-INST: fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s
// CHECK-ENCODING: [0x4d,0x59,0x25,0xc1]
@@ -290,6 +447,157 @@ fmls za.s[w9, 7], {z12.s - z13.s}, z11.s // 11000001-00101011-00111001-10001
// CHECK-UNKNOWN: c12b398f <unknown>
+fmls za.s[w8, 0, vgx2], {z0.s, z1.s}, {z0.s, z1.s} // 11000001, 10100000, 00011000, 00001000
+// CHECK-INST: fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x08,0x18,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01808 <unknown>
+
+fmls za.s[w8, 0], {z0.s - z1.s}, {z0.s - z1.s} // 11000001-10100000-00011000-00001000
+// CHECK-INST: fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x08,0x18,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01808 <unknown>
+
+fmls za.s[w10, 5, vgx2], {z10.s, z11.s}, {z20.s, z21.s} // 11000001, 10110100, 01011001, 01001101
+// CHECK-INST: fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x4d,0x59,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4594d <unknown>
+
+fmls za.s[w10, 5], {z10.s - z11.s}, {z20.s - z21.s} // 11000001-10110100-01011001-01001101
+// CHECK-INST: fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x4d,0x59,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4594d <unknown>
+
+fmls za.s[w11, 7, vgx2], {z12.s, z13.s}, {z8.s, z9.s} // 11000001, 10101000, 01111001, 10001111
+// CHECK-INST: fmls za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x8f,0x79,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8798f <unknown>
+
+fmls za.s[w11, 7], {z12.s - z13.s}, {z8.s - z9.s} // 11000001-10101000-01111001-10001111
+// CHECK-INST: fmls za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x8f,0x79,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8798f <unknown>
+
+fmls za.s[w11, 7, vgx2], {z30.s, z31.s}, {z30.s, z31.s} // 11000001, 10111110, 01111011, 11001111
+// CHECK-INST: fmls za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xcf,0x7b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be7bcf <unknown>
+
+fmls za.s[w11, 7], {z30.s - z31.s}, {z30.s - z31.s} // 11000001-10111110-01111011-11001111
+// CHECK-INST: fmls za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xcf,0x7b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be7bcf <unknown>
+
+fmls za.s[w8, 5, vgx2], {z16.s, z17.s}, {z16.s, z17.s} // 11000001, 10110000, 00011010, 00001101
+// CHECK-INST: fmls za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }
+// CHECK-ENCODING: [0x0d,0x1a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b01a0d <unknown>
+
+fmls za.s[w8, 5], {z16.s - z17.s}, {z16.s - z17.s} // 11000001-10110000-00011010-00001101
+// CHECK-INST: fmls za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }
+// CHECK-ENCODING: [0x0d,0x1a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b01a0d <unknown>
+
+fmls za.s[w8, 1, vgx2], {z0.s, z1.s}, {z30.s, z31.s} // 11000001, 10111110, 00011000, 00001001
+// CHECK-INST: fmls za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x09,0x18,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1809 <unknown>
+
+fmls za.s[w8, 1], {z0.s - z1.s}, {z30.s - z31.s} // 11000001-10111110-00011000-00001001
+// CHECK-INST: fmls za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x09,0x18,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1809 <unknown>
+
+fmls za.s[w10, 0, vgx2], {z18.s, z19.s}, {z20.s, z21.s} // 11000001, 10110100, 01011010, 01001000
+// CHECK-INST: fmls za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x48,0x5a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b45a48 <unknown>
+
+fmls za.s[w10, 0], {z18.s - z19.s}, {z20.s - z21.s} // 11000001-10110100-01011010-01001000
+// CHECK-INST: fmls za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x48,0x5a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b45a48 <unknown>
+
+fmls za.s[w8, 0, vgx2], {z12.s, z13.s}, {z2.s, z3.s} // 11000001, 10100010, 00011001, 10001000
+// CHECK-INST: fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }
+// CHECK-ENCODING: [0x88,0x19,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a21988 <unknown>
+
+fmls za.s[w8, 0], {z12.s - z13.s}, {z2.s - z3.s} // 11000001-10100010-00011001-10001000
+// CHECK-INST: fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }
+// CHECK-ENCODING: [0x88,0x19,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a21988 <unknown>
+
+fmls za.s[w10, 1, vgx2], {z0.s, z1.s}, {z26.s, z27.s} // 11000001, 10111010, 01011000, 00001001
+// CHECK-INST: fmls za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }
+// CHECK-ENCODING: [0x09,0x58,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba5809 <unknown>
+
+fmls za.s[w10, 1], {z0.s - z1.s}, {z26.s - z27.s} // 11000001-10111010-01011000-00001001
+// CHECK-INST: fmls za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }
+// CHECK-ENCODING: [0x09,0x58,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba5809 <unknown>
+
+fmls za.s[w8, 5, vgx2], {z22.s, z23.s}, {z30.s, z31.s} // 11000001, 10111110, 00011010, 11001101
+// CHECK-INST: fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xcd,0x1a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1acd <unknown>
+
+fmls za.s[w8, 5], {z22.s - z23.s}, {z30.s - z31.s} // 11000001-10111110-00011010-11001101
+// CHECK-INST: fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xcd,0x1a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1acd <unknown>
+
+fmls za.s[w11, 2, vgx2], {z8.s, z9.s}, {z0.s, z1.s} // 11000001, 10100000, 01111001, 00001010
+// CHECK-INST: fmls za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x0a,0x79,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0790a <unknown>
+
+fmls za.s[w11, 2], {z8.s - z9.s}, {z0.s - z1.s} // 11000001-10100000-01111001-00001010
+// CHECK-INST: fmls za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x0a,0x79,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0790a <unknown>
+
+fmls za.s[w9, 7, vgx2], {z12.s, z13.s}, {z10.s, z11.s} // 11000001, 10101010, 00111001, 10001111
+// CHECK-INST: fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x8f,0x39,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa398f <unknown>
+
+fmls za.s[w9, 7], {z12.s - z13.s}, {z10.s - z11.s} // 11000001-10101010-00111001-10001111
+// CHECK-INST: fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x8f,0x39,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa398f <unknown>
+
+
+fmls za.d[w8, 0, vgx4], {z0.d - z3.d}, z0.d // 11000001-01110000-00011000-00001000
+// CHECK-INST: fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x08,0x18,0x70,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1701808 <unknown>
+
fmls za.d[w8, 0], {z0.d - z3.d}, z0.d // 11000001-01110000-00011000-00001000
// CHECK-INST: fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d
// CHECK-ENCODING: [0x08,0x18,0x70,0xc1]
@@ -429,6 +737,151 @@ fmls za.d[w9, 7], {z12.d - z15.d}, z11.d // 11000001-01111011-00111001-10001
// CHECK-UNKNOWN: c17b398f <unknown>
+fmls za.d[w8, 0, vgx4], {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100001-00011000-00001000
+// CHECK-INST: fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x08,0x18,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11808 <unknown>
+
+fmls za.d[w8, 0], {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100001-00011000-00001000
+// CHECK-INST: fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x08,0x18,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11808 <unknown>
+
+fmls za.d[w10, 5, vgx4], {z8.d - z11.d}, {z20.d - z23.d} // 11000001-11110101-01011001-00001101
+// CHECK-INST: fmls za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x0d,0x59,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5590d <unknown>
+
+fmls za.d[w10, 5], {z8.d - z11.d}, {z20.d - z23.d} // 11000001-11110101-01011001-00001101
+// CHECK-INST: fmls za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x0d,0x59,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5590d <unknown>
+
+fmls za.d[w11, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-01111001-10001111
+// CHECK-INST: fmls za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x8f,0x79,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9798f <unknown>
+
+fmls za.d[w11, 7], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-01111001-10001111
+// CHECK-INST: fmls za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x8f,0x79,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9798f <unknown>
+
+fmls za.d[w11, 7, vgx4], {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111101-01111011-10001111
+// CHECK-INST: fmls za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x8f,0x7b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd7b8f <unknown>
+
+fmls za.d[w11, 7], {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111101-01111011-10001111
+// CHECK-INST: fmls za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x8f,0x7b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd7b8f <unknown>
+
+fmls za.d[w8, 5, vgx4], {z16.d - z19.d}, {z16.d - z19.d} // 11000001-11110001-00011010-00001101
+// CHECK-INST: fmls za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }
+// CHECK-ENCODING: [0x0d,0x1a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f11a0d <unknown>
+
+fmls za.d[w8, 5], {z16.d - z19.d}, {z16.d - z19.d} // 11000001-11110001-00011010-00001101
+// CHECK-INST: fmls za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }
+// CHECK-ENCODING: [0x0d,0x1a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f11a0d <unknown>
+
+fmls za.d[w8, 1, vgx4], {z0.d - z3.d}, {z28.d - z31.d} // 11000001-11111101-00011000-00001001
+// CHECK-INST: fmls za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x09,0x18,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1809 <unknown>
+
+fmls za.d[w8, 1], {z0.d - z3.d}, {z28.d - z31.d} // 11000001-11111101-00011000-00001001
+// CHECK-INST: fmls za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x09,0x18,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1809 <unknown>
+
+fmls za.d[w10, 0, vgx4], {z16.d - z19.d}, {z20.d - z23.d} // 11000001-11110101-01011010-00001000
+// CHECK-INST: fmls za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x08,0x5a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55a08 <unknown>
+
+fmls za.d[w10, 0], {z16.d - z19.d}, {z20.d - z23.d} // 11000001-11110101-01011010-00001000
+// CHECK-INST: fmls za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x08,0x5a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55a08 <unknown>
+
+fmls za.d[w8, 0, vgx4], {z12.d - z15.d}, {z0.d - z3.d} // 11000001-11100001-00011001-10001000
+// CHECK-INST: fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x88,0x19,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11988 <unknown>
+
+fmls za.d[w8, 0], {z12.d - z15.d}, {z0.d - z3.d} // 11000001-11100001-00011001-10001000
+// CHECK-INST: fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x88,0x19,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11988 <unknown>
+
+fmls za.d[w10, 1, vgx4], {z0.d - z3.d}, {z24.d - z27.d} // 11000001-11111001-01011000-00001001
+// CHECK-INST: fmls za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }
+// CHECK-ENCODING: [0x09,0x58,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f95809 <unknown>
+
+fmls za.d[w10, 1], {z0.d - z3.d}, {z24.d - z27.d} // 11000001-11111001-01011000-00001001
+// CHECK-INST: fmls za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }
+// CHECK-ENCODING: [0x09,0x58,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f95809 <unknown>
+
+fmls za.d[w8, 5, vgx4], {z20.d - z23.d}, {z28.d - z31.d} // 11000001-11111101-00011010-10001101
+// CHECK-INST: fmls za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x8d,0x1a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1a8d <unknown>
+
+fmls za.d[w8, 5], {z20.d - z23.d}, {z28.d - z31.d} // 11000001-11111101-00011010-10001101
+// CHECK-INST: fmls za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x8d,0x1a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1a8d <unknown>
+
+fmls za.d[w11, 2, vgx4], {z8.d - z11.d}, {z0.d - z3.d} // 11000001-11100001-01111001-00001010
+// CHECK-INST: fmls za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x0a,0x79,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e1790a <unknown>
+
+fmls za.d[w11, 2], {z8.d - z11.d}, {z0.d - z3.d} // 11000001-11100001-01111001-00001010
+// CHECK-INST: fmls za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x0a,0x79,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e1790a <unknown>
+
+fmls za.d[w9, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-00111001-10001111
+// CHECK-INST: fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x8f,0x39,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9398f <unknown>
+
+fmls za.d[w9, 7], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-00111001-10001111
+// CHECK-INST: fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x8f,0x39,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9398f <unknown>
+
+
fmls za.s[w8, 0, vgx4], {z0.s - z3.s}, z0.s // 11000001-00110000-00011000-00001000
// CHECK-INST: fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
// CHECK-ENCODING: [0x08,0x18,0x30,0xc1]
@@ -573,3 +1026,148 @@ fmls za.s[w9, 7], {z12.s - z15.s}, z11.s // 11000001-00111011-00111001-10001
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13b398f <unknown>
+
+fmls za.s[w8, 0, vgx4], {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100001-00011000-00001000
+// CHECK-INST: fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x08,0x18,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11808 <unknown>
+
+fmls za.s[w8, 0], {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100001-00011000-00001000
+// CHECK-INST: fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x08,0x18,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11808 <unknown>
+
+fmls za.s[w10, 5, vgx4], {z8.s - z11.s}, {z20.s - z23.s} // 11000001-10110101-01011001-00001101
+// CHECK-INST: fmls za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x0d,0x59,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5590d <unknown>
+
+fmls za.s[w10, 5], {z8.s - z11.s}, {z20.s - z23.s} // 11000001-10110101-01011001-00001101
+// CHECK-INST: fmls za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x0d,0x59,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5590d <unknown>
+
+fmls za.s[w11, 7, vgx4], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-01111001-10001111
+// CHECK-INST: fmls za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x8f,0x79,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9798f <unknown>
+
+fmls za.s[w11, 7], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-01111001-10001111
+// CHECK-INST: fmls za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x8f,0x79,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9798f <unknown>
+
+fmls za.s[w11, 7, vgx4], {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111101-01111011-10001111
+// CHECK-INST: fmls za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x8f,0x7b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd7b8f <unknown>
+
+fmls za.s[w11, 7], {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111101-01111011-10001111
+// CHECK-INST: fmls za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x8f,0x7b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd7b8f <unknown>
+
+fmls za.s[w8, 5, vgx4], {z16.s - z19.s}, {z16.s - z19.s} // 11000001-10110001-00011010-00001101
+// CHECK-INST: fmls za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }
+// CHECK-ENCODING: [0x0d,0x1a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b11a0d <unknown>
+
+fmls za.s[w8, 5], {z16.s - z19.s}, {z16.s - z19.s} // 11000001-10110001-00011010-00001101
+// CHECK-INST: fmls za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }
+// CHECK-ENCODING: [0x0d,0x1a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b11a0d <unknown>
+
+fmls za.s[w8, 1, vgx4], {z0.s - z3.s}, {z28.s - z31.s} // 11000001-10111101-00011000-00001001
+// CHECK-INST: fmls za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x09,0x18,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1809 <unknown>
+
+fmls za.s[w8, 1], {z0.s - z3.s}, {z28.s - z31.s} // 11000001-10111101-00011000-00001001
+// CHECK-INST: fmls za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x09,0x18,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1809 <unknown>
+
+fmls za.s[w10, 0, vgx4], {z16.s - z19.s}, {z20.s - z23.s} // 11000001-10110101-01011010-00001000
+// CHECK-INST: fmls za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x08,0x5a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b55a08 <unknown>
+
+fmls za.s[w10, 0], {z16.s - z19.s}, {z20.s - z23.s} // 11000001-10110101-01011010-00001000
+// CHECK-INST: fmls za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x08,0x5a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b55a08 <unknown>
+
+fmls za.s[w8, 0, vgx4], {z12.s - z15.s}, {z0.s - z3.s} // 11000001-10100001-00011001-10001000
+// CHECK-INST: fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x88,0x19,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11988 <unknown>
+
+fmls za.s[w8, 0], {z12.s - z15.s}, {z0.s - z3.s} // 11000001-10100001-00011001-10001000
+// CHECK-INST: fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x88,0x19,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11988 <unknown>
+
+fmls za.s[w10, 1, vgx4], {z0.s - z3.s}, {z24.s - z27.s} // 11000001-10111001-01011000-00001001
+// CHECK-INST: fmls za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }
+// CHECK-ENCODING: [0x09,0x58,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b95809 <unknown>
+
+fmls za.s[w10, 1], {z0.s - z3.s}, {z24.s - z27.s} // 11000001-10111001-01011000-00001001
+// CHECK-INST: fmls za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }
+// CHECK-ENCODING: [0x09,0x58,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b95809 <unknown>
+
+fmls za.s[w8, 5, vgx4], {z20.s - z23.s}, {z28.s - z31.s} // 11000001-10111101-00011010-10001101
+// CHECK-INST: fmls za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x8d,0x1a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1a8d <unknown>
+
+fmls za.s[w8, 5], {z20.s - z23.s}, {z28.s - z31.s} // 11000001-10111101-00011010-10001101
+// CHECK-INST: fmls za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x8d,0x1a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1a8d <unknown>
+
+fmls za.s[w11, 2, vgx4], {z8.s - z11.s}, {z0.s - z3.s} // 11000001-10100001-01111001-00001010
+// CHECK-INST: fmls za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x0a,0x79,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a1790a <unknown>
+
+fmls za.s[w11, 2], {z8.s - z11.s}, {z0.s - z3.s} // 11000001-10100001-01111001-00001010
+// CHECK-INST: fmls za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x0a,0x79,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a1790a <unknown>
+
+fmls za.s[w9, 7, vgx4], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-00111001-10001111
+// CHECK-INST: fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x8f,0x39,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9398f <unknown>
+
+fmls za.s[w9, 7], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-00111001-10001111
+// CHECK-INST: fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x8f,0x39,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9398f <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/sub-diagnostics.s b/llvm/test/MC/AArch64/SME2/sub-diagnostics.s
index 2c8dcb325bae7..4a7e7b20236fa 100644
--- a/llvm/test/MC/AArch64/SME2/sub-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2/sub-diagnostics.s
@@ -48,3 +48,30 @@ sub za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
// CHECK-NEXT: za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+sub za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: sub za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sub za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: sub za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sub za.d[w11, 7, vgx4], {z12.d-z15.d}, {z9.d-z12.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: sub za.d[w11, 7, vgx4], {z12.d-z15.d}, {z9.d-z12.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sub za.s[w10, 3], {z10.b-z11.b}, {z20.b-z21.b}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sub za.s[w10, 3], {z10.b-z11.b}, {z20.b-z21.b}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sub za.d[w11, 7], {z28.h - z31.h}, {z28.h - z31.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sub za.d[w11, 7], {z28.h - z31.h}, {z28.h - z31.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/sub.s b/llvm/test/MC/AArch64/SME2/sub.s
index 0ca5c3ba4ccd8..f2474bd7b68f6 100644
--- a/llvm/test/MC/AArch64/SME2/sub.s
+++ b/llvm/test/MC/AArch64/SME2/sub.s
@@ -157,6 +157,151 @@ sub za.s[w9, 7], {z12.s - z13.s}, z11.s // 11000001-00101011-00111001-10011
// CHECK-UNKNOWN: c12b399f <unknown>
+sub za.s[w8, 0, vgx2], {z0.s, z1.s}, {z0.s, z1.s} // 11000001, 10100000, 00011000, 00011000
+// CHECK-INST: sub za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x18,0x18,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01818 <unknown>
+
+sub za.s[w8, 0], {z0.s - z1.s}, {z0.s - z1.s} // 11000001-10100000-00011000-00011000
+// CHECK-INST: sub za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x18,0x18,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a01818 <unknown>
+
+sub za.s[w10, 5, vgx2], {z10.s, z11.s}, {z20.s, z21.s} // 11000001, 10110100, 01011001, 01011101
+// CHECK-INST: sub za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x5d,0x59,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4595d <unknown>
+
+sub za.s[w10, 5], {z10.s - z11.s}, {z20.s - z21.s} // 11000001-10110100-01011001-01011101
+// CHECK-INST: sub za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x5d,0x59,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b4595d <unknown>
+
+sub za.s[w11, 7, vgx2], {z12.s, z13.s}, {z8.s, z9.s} // 11000001, 10101000, 01111001, 10011111
+// CHECK-INST: sub za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x9f,0x79,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8799f <unknown>
+
+sub za.s[w11, 7], {z12.s - z13.s}, {z8.s - z9.s} // 11000001-10101000-01111001-10011111
+// CHECK-INST: sub za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }
+// CHECK-ENCODING: [0x9f,0x79,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8799f <unknown>
+
+sub za.s[w11, 7, vgx2], {z30.s, z31.s}, {z30.s, z31.s} // 11000001, 10111110, 01111011, 11011111
+// CHECK-INST: sub za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xdf,0x7b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be7bdf <unknown>
+
+sub za.s[w11, 7], {z30.s - z31.s}, {z30.s - z31.s} // 11000001-10111110-01111011-11011111
+// CHECK-INST: sub za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xdf,0x7b,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be7bdf <unknown>
+
+sub za.s[w8, 5, vgx2], {z16.s, z17.s}, {z16.s, z17.s} // 11000001, 10110000, 00011010, 00011101
+// CHECK-INST: sub za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }
+// CHECK-ENCODING: [0x1d,0x1a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b01a1d <unknown>
+
+sub za.s[w8, 5], {z16.s - z17.s}, {z16.s - z17.s} // 11000001-10110000-00011010-00011101
+// CHECK-INST: sub za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }
+// CHECK-ENCODING: [0x1d,0x1a,0xb0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b01a1d <unknown>
+
+sub za.s[w8, 1, vgx2], {z0.s, z1.s}, {z30.s, z31.s} // 11000001, 10111110, 00011000, 00011001
+// CHECK-INST: sub za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x19,0x18,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1819 <unknown>
+
+sub za.s[w8, 1], {z0.s - z1.s}, {z30.s - z31.s} // 11000001-10111110-00011000-00011001
+// CHECK-INST: sub za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0x19,0x18,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1819 <unknown>
+
+sub za.s[w10, 0, vgx2], {z18.s, z19.s}, {z20.s, z21.s} // 11000001, 10110100, 01011010, 01011000
+// CHECK-INST: sub za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x58,0x5a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b45a58 <unknown>
+
+sub za.s[w10, 0], {z18.s - z19.s}, {z20.s - z21.s} // 11000001-10110100-01011010-01011000
+// CHECK-INST: sub za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x58,0x5a,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b45a58 <unknown>
+
+sub za.s[w8, 0, vgx2], {z12.s, z13.s}, {z2.s, z3.s} // 11000001, 10100010, 00011001, 10011000
+// CHECK-INST: sub za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }
+// CHECK-ENCODING: [0x98,0x19,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a21998 <unknown>
+
+sub za.s[w8, 0], {z12.s - z13.s}, {z2.s - z3.s} // 11000001-10100010-00011001-10011000
+// CHECK-INST: sub za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }
+// CHECK-ENCODING: [0x98,0x19,0xa2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a21998 <unknown>
+
+sub za.s[w10, 1, vgx2], {z0.s, z1.s}, {z26.s, z27.s} // 11000001, 10111010, 01011000, 00011001
+// CHECK-INST: sub za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }
+// CHECK-ENCODING: [0x19,0x58,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba5819 <unknown>
+
+sub za.s[w10, 1], {z0.s - z1.s}, {z26.s - z27.s} // 11000001-10111010-01011000-00011001
+// CHECK-INST: sub za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }
+// CHECK-ENCODING: [0x19,0x58,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ba5819 <unknown>
+
+sub za.s[w8, 5, vgx2], {z22.s, z23.s}, {z30.s, z31.s} // 11000001, 10111110, 00011010, 11011101
+// CHECK-INST: sub za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xdd,0x1a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1add <unknown>
+
+sub za.s[w8, 5], {z22.s - z23.s}, {z30.s - z31.s} // 11000001-10111110-00011010-11011101
+// CHECK-INST: sub za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xdd,0x1a,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1be1add <unknown>
+
+sub za.s[w11, 2, vgx2], {z8.s, z9.s}, {z0.s, z1.s} // 11000001, 10100000, 01111001, 00011010
+// CHECK-INST: sub za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x1a,0x79,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0791a <unknown>
+
+sub za.s[w11, 2], {z8.s - z9.s}, {z0.s - z1.s} // 11000001-10100000-01111001-00011010
+// CHECK-INST: sub za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x1a,0x79,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0791a <unknown>
+
+sub za.s[w9, 7, vgx2], {z12.s, z13.s}, {z10.s, z11.s} // 11000001, 10101010, 00111001, 10011111
+// CHECK-INST: sub za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x9f,0x39,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa399f <unknown>
+
+sub za.s[w9, 7], {z12.s - z13.s}, {z10.s - z11.s} // 11000001-10101010-00111001-10011111
+// CHECK-INST: sub za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x9f,0x39,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aa399f <unknown>
+
+
sub za.d[w8, 0, vgx2], {z0.d, z1.d}, z0.d // 11000001, 01100000, 00011000, 00011000
// CHECK-INST: sub za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d
// CHECK-ENCODING: [0x18,0x18,0x60,0xc1]
@@ -302,6 +447,151 @@ sub za.d[w9, 7], {z12.d - z13.d}, z11.d // 11000001-01101011-00111001-10011
// CHECK-UNKNOWN: c16b399f <unknown>
+sub za.d[w8, 0, vgx2], {z0.d, z1.d}, {z0.d, z1.d} // 11000001, 11100000, 00011000, 00011000
+// CHECK-INST: sub za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x18,0x18,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01818 <unknown>
+
+sub za.d[w8, 0], {z0.d - z1.d}, {z0.d - z1.d} // 11000001-11100000-00011000-00011000
+// CHECK-INST: sub za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x18,0x18,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e01818 <unknown>
+
+sub za.d[w10, 5, vgx2], {z10.d, z11.d}, {z20.d, z21.d} // 11000001, 11110100, 01011001, 01011101
+// CHECK-INST: sub za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x5d,0x59,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4595d <unknown>
+
+sub za.d[w10, 5], {z10.d - z11.d}, {z20.d - z21.d} // 11000001-11110100-01011001-01011101
+// CHECK-INST: sub za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x5d,0x59,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f4595d <unknown>
+
+sub za.d[w11, 7, vgx2], {z12.d, z13.d}, {z8.d, z9.d} // 11000001, 11101000, 01111001, 10011111
+// CHECK-INST: sub za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x9f,0x79,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8799f <unknown>
+
+sub za.d[w11, 7], {z12.d - z13.d}, {z8.d - z9.d} // 11000001-11101000-01111001-10011111
+// CHECK-INST: sub za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }
+// CHECK-ENCODING: [0x9f,0x79,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8799f <unknown>
+
+sub za.d[w11, 7, vgx2], {z30.d, z31.d}, {z30.d, z31.d} // 11000001, 11111110, 01111011, 11011111
+// CHECK-INST: sub za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xdf,0x7b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe7bdf <unknown>
+
+sub za.d[w11, 7], {z30.d - z31.d}, {z30.d - z31.d} // 11000001-11111110-01111011-11011111
+// CHECK-INST: sub za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xdf,0x7b,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe7bdf <unknown>
+
+sub za.d[w8, 5, vgx2], {z16.d, z17.d}, {z16.d, z17.d} // 11000001, 11110000, 00011010, 00011101
+// CHECK-INST: sub za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }
+// CHECK-ENCODING: [0x1d,0x1a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f01a1d <unknown>
+
+sub za.d[w8, 5], {z16.d - z17.d}, {z16.d - z17.d} // 11000001-11110000-00011010-00011101
+// CHECK-INST: sub za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }
+// CHECK-ENCODING: [0x1d,0x1a,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f01a1d <unknown>
+
+sub za.d[w8, 1, vgx2], {z0.d, z1.d}, {z30.d, z31.d} // 11000001, 11111110, 00011000, 00011001
+// CHECK-INST: sub za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x19,0x18,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1819 <unknown>
+
+sub za.d[w8, 1], {z0.d - z1.d}, {z30.d - z31.d} // 11000001-11111110-00011000-00011001
+// CHECK-INST: sub za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0x19,0x18,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1819 <unknown>
+
+sub za.d[w10, 0, vgx2], {z18.d, z19.d}, {z20.d, z21.d} // 11000001, 11110100, 01011010, 01011000
+// CHECK-INST: sub za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x58,0x5a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f45a58 <unknown>
+
+sub za.d[w10, 0], {z18.d - z19.d}, {z20.d - z21.d} // 11000001-11110100-01011010-01011000
+// CHECK-INST: sub za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x58,0x5a,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f45a58 <unknown>
+
+sub za.d[w8, 0, vgx2], {z12.d, z13.d}, {z2.d, z3.d} // 11000001, 11100010, 00011001, 10011000
+// CHECK-INST: sub za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }
+// CHECK-ENCODING: [0x98,0x19,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e21998 <unknown>
+
+sub za.d[w8, 0], {z12.d - z13.d}, {z2.d - z3.d} // 11000001-11100010-00011001-10011000
+// CHECK-INST: sub za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }
+// CHECK-ENCODING: [0x98,0x19,0xe2,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e21998 <unknown>
+
+sub za.d[w10, 1, vgx2], {z0.d, z1.d}, {z26.d, z27.d} // 11000001, 11111010, 01011000, 00011001
+// CHECK-INST: sub za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }
+// CHECK-ENCODING: [0x19,0x58,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa5819 <unknown>
+
+sub za.d[w10, 1], {z0.d - z1.d}, {z26.d - z27.d} // 11000001-11111010-01011000-00011001
+// CHECK-INST: sub za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }
+// CHECK-ENCODING: [0x19,0x58,0xfa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fa5819 <unknown>
+
+sub za.d[w8, 5, vgx2], {z22.d, z23.d}, {z30.d, z31.d} // 11000001, 11111110, 00011010, 11011101
+// CHECK-INST: sub za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xdd,0x1a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1add <unknown>
+
+sub za.d[w8, 5], {z22.d - z23.d}, {z30.d - z31.d} // 11000001-11111110-00011010-11011101
+// CHECK-INST: sub za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xdd,0x1a,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fe1add <unknown>
+
+sub za.d[w11, 2, vgx2], {z8.d, z9.d}, {z0.d, z1.d} // 11000001, 11100000, 01111001, 00011010
+// CHECK-INST: sub za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x1a,0x79,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0791a <unknown>
+
+sub za.d[w11, 2], {z8.d - z9.d}, {z0.d - z1.d} // 11000001-11100000-01111001-00011010
+// CHECK-INST: sub za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x1a,0x79,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0791a <unknown>
+
+sub za.d[w9, 7, vgx2], {z12.d, z13.d}, {z10.d, z11.d} // 11000001, 11101010, 00111001, 10011111
+// CHECK-INST: sub za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }
+// CHECK-ENCODING: [0x9f,0x39,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea399f <unknown>
+
+sub za.d[w9, 7], {z12.d - z13.d}, {z10.d - z11.d} // 11000001-11101010-00111001-10011111
+// CHECK-INST: sub za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }
+// CHECK-ENCODING: [0x9f,0x39,0xea,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ea399f <unknown>
+
+
sub za.s[w8, 0, vgx4], {z0.s - z3.s}, z0.s // 11000001-00110000-00011000-00011000
// CHECK-INST: sub za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
// CHECK-ENCODING: [0x18,0x18,0x30,0xc1]
@@ -447,6 +737,151 @@ sub za.s[w9, 7], {z12.s - z15.s}, z11.s // 11000001-00111011-00111001-10011
// CHECK-UNKNOWN: c13b399f <unknown>
+sub za.s[w8, 0, vgx4], {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100001-00011000-00011000
+// CHECK-INST: sub za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x18,0x18,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11818 <unknown>
+
+sub za.s[w8, 0], {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100001-00011000-00011000
+// CHECK-INST: sub za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x18,0x18,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11818 <unknown>
+
+sub za.s[w10, 5, vgx4], {z8.s - z11.s}, {z20.s - z23.s} // 11000001-10110101-01011001-00011101
+// CHECK-INST: sub za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x1d,0x59,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5591d <unknown>
+
+sub za.s[w10, 5], {z8.s - z11.s}, {z20.s - z23.s} // 11000001-10110101-01011001-00011101
+// CHECK-INST: sub za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x1d,0x59,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5591d <unknown>
+
+sub za.s[w11, 7, vgx4], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-01111001-10011111
+// CHECK-INST: sub za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x9f,0x79,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9799f <unknown>
+
+sub za.s[w11, 7], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-01111001-10011111
+// CHECK-INST: sub za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x9f,0x79,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9799f <unknown>
+
+sub za.s[w11, 7, vgx4], {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111101-01111011-10011111
+// CHECK-INST: sub za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x9f,0x7b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd7b9f <unknown>
+
+sub za.s[w11, 7], {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111101-01111011-10011111
+// CHECK-INST: sub za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x9f,0x7b,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd7b9f <unknown>
+
+sub za.s[w8, 5, vgx4], {z16.s - z19.s}, {z16.s - z19.s} // 11000001-10110001-00011010-00011101
+// CHECK-INST: sub za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }
+// CHECK-ENCODING: [0x1d,0x1a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b11a1d <unknown>
+
+sub za.s[w8, 5], {z16.s - z19.s}, {z16.s - z19.s} // 11000001-10110001-00011010-00011101
+// CHECK-INST: sub za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }
+// CHECK-ENCODING: [0x1d,0x1a,0xb1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b11a1d <unknown>
+
+sub za.s[w8, 1, vgx4], {z0.s - z3.s}, {z28.s - z31.s} // 11000001-10111101-00011000-00011001
+// CHECK-INST: sub za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x19,0x18,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1819 <unknown>
+
+sub za.s[w8, 1], {z0.s - z3.s}, {z28.s - z31.s} // 11000001-10111101-00011000-00011001
+// CHECK-INST: sub za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x19,0x18,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1819 <unknown>
+
+sub za.s[w10, 0, vgx4], {z16.s - z19.s}, {z20.s - z23.s} // 11000001-10110101-01011010-00011000
+// CHECK-INST: sub za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x18,0x5a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b55a18 <unknown>
+
+sub za.s[w10, 0], {z16.s - z19.s}, {z20.s - z23.s} // 11000001-10110101-01011010-00011000
+// CHECK-INST: sub za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x18,0x5a,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b55a18 <unknown>
+
+sub za.s[w8, 0, vgx4], {z12.s - z15.s}, {z0.s - z3.s} // 11000001-10100001-00011001-10011000
+// CHECK-INST: sub za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x98,0x19,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11998 <unknown>
+
+sub za.s[w8, 0], {z12.s - z15.s}, {z0.s - z3.s} // 11000001-10100001-00011001-10011000
+// CHECK-INST: sub za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x98,0x19,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11998 <unknown>
+
+sub za.s[w10, 1, vgx4], {z0.s - z3.s}, {z24.s - z27.s} // 11000001-10111001-01011000-00011001
+// CHECK-INST: sub za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }
+// CHECK-ENCODING: [0x19,0x58,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b95819 <unknown>
+
+sub za.s[w10, 1], {z0.s - z3.s}, {z24.s - z27.s} // 11000001-10111001-01011000-00011001
+// CHECK-INST: sub za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }
+// CHECK-ENCODING: [0x19,0x58,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b95819 <unknown>
+
+sub za.s[w8, 5, vgx4], {z20.s - z23.s}, {z28.s - z31.s} // 11000001-10111101-00011010-10011101
+// CHECK-INST: sub za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x9d,0x1a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1a9d <unknown>
+
+sub za.s[w8, 5], {z20.s - z23.s}, {z28.s - z31.s} // 11000001-10111101-00011010-10011101
+// CHECK-INST: sub za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x9d,0x1a,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bd1a9d <unknown>
+
+sub za.s[w11, 2, vgx4], {z8.s - z11.s}, {z0.s - z3.s} // 11000001-10100001-01111001-00011010
+// CHECK-INST: sub za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x1a,0x79,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a1791a <unknown>
+
+sub za.s[w11, 2], {z8.s - z11.s}, {z0.s - z3.s} // 11000001-10100001-01111001-00011010
+// CHECK-INST: sub za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x1a,0x79,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a1791a <unknown>
+
+sub za.s[w9, 7, vgx4], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-00111001-10011111
+// CHECK-INST: sub za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x9f,0x39,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9399f <unknown>
+
+sub za.s[w9, 7], {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-00111001-10011111
+// CHECK-INST: sub za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x9f,0x39,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9399f <unknown>
+
+
sub za.d[w8, 0, vgx4], {z0.d - z3.d}, z0.d // 11000001-01110000-00011000-00011000
// CHECK-INST: sub za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d
// CHECK-ENCODING: [0x18,0x18,0x70,0xc1]
@@ -591,3 +1026,148 @@ sub za.d[w9, 7], {z12.d - z15.d}, z11.d // 11000001-01111011-00111001-10011
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17b399f <unknown>
+
+sub za.d[w8, 0, vgx4], {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100001-00011000-00011000
+// CHECK-INST: sub za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x18,0x18,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11818 <unknown>
+
+sub za.d[w8, 0], {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100001-00011000-00011000
+// CHECK-INST: sub za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x18,0x18,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11818 <unknown>
+
+sub za.d[w10, 5, vgx4], {z8.d - z11.d}, {z20.d - z23.d} // 11000001-11110101-01011001-00011101
+// CHECK-INST: sub za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x1d,0x59,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5591d <unknown>
+
+sub za.d[w10, 5], {z8.d - z11.d}, {z20.d - z23.d} // 11000001-11110101-01011001-00011101
+// CHECK-INST: sub za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x1d,0x59,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5591d <unknown>
+
+sub za.d[w11, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-01111001-10011111
+// CHECK-INST: sub za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x9f,0x79,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9799f <unknown>
+
+sub za.d[w11, 7], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-01111001-10011111
+// CHECK-INST: sub za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x9f,0x79,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9799f <unknown>
+
+sub za.d[w11, 7, vgx4], {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111101-01111011-10011111
+// CHECK-INST: sub za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x9f,0x7b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd7b9f <unknown>
+
+sub za.d[w11, 7], {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111101-01111011-10011111
+// CHECK-INST: sub za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x9f,0x7b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd7b9f <unknown>
+
+sub za.d[w8, 5, vgx4], {z16.d - z19.d}, {z16.d - z19.d} // 11000001-11110001-00011010-00011101
+// CHECK-INST: sub za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }
+// CHECK-ENCODING: [0x1d,0x1a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f11a1d <unknown>
+
+sub za.d[w8, 5], {z16.d - z19.d}, {z16.d - z19.d} // 11000001-11110001-00011010-00011101
+// CHECK-INST: sub za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }
+// CHECK-ENCODING: [0x1d,0x1a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f11a1d <unknown>
+
+sub za.d[w8, 1, vgx4], {z0.d - z3.d}, {z28.d - z31.d} // 11000001-11111101-00011000-00011001
+// CHECK-INST: sub za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x19,0x18,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1819 <unknown>
+
+sub za.d[w8, 1], {z0.d - z3.d}, {z28.d - z31.d} // 11000001-11111101-00011000-00011001
+// CHECK-INST: sub za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x19,0x18,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1819 <unknown>
+
+sub za.d[w10, 0, vgx4], {z16.d - z19.d}, {z20.d - z23.d} // 11000001-11110101-01011010-00011000
+// CHECK-INST: sub za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x18,0x5a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55a18 <unknown>
+
+sub za.d[w10, 0], {z16.d - z19.d}, {z20.d - z23.d} // 11000001-11110101-01011010-00011000
+// CHECK-INST: sub za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x18,0x5a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55a18 <unknown>
+
+sub za.d[w8, 0, vgx4], {z12.d - z15.d}, {z0.d - z3.d} // 11000001-11100001-00011001-10011000
+// CHECK-INST: sub za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x98,0x19,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11998 <unknown>
+
+sub za.d[w8, 0], {z12.d - z15.d}, {z0.d - z3.d} // 11000001-11100001-00011001-10011000
+// CHECK-INST: sub za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x98,0x19,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11998 <unknown>
+
+sub za.d[w10, 1, vgx4], {z0.d - z3.d}, {z24.d - z27.d} // 11000001-11111001-01011000-00011001
+// CHECK-INST: sub za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }
+// CHECK-ENCODING: [0x19,0x58,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f95819 <unknown>
+
+sub za.d[w10, 1], {z0.d - z3.d}, {z24.d - z27.d} // 11000001-11111001-01011000-00011001
+// CHECK-INST: sub za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }
+// CHECK-ENCODING: [0x19,0x58,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f95819 <unknown>
+
+sub za.d[w8, 5, vgx4], {z20.d - z23.d}, {z28.d - z31.d} // 11000001-11111101-00011010-10011101
+// CHECK-INST: sub za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x9d,0x1a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1a9d <unknown>
+
+sub za.d[w8, 5], {z20.d - z23.d}, {z28.d - z31.d} // 11000001-11111101-00011010-10011101
+// CHECK-INST: sub za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x9d,0x1a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1a9d <unknown>
+
+sub za.d[w11, 2, vgx4], {z8.d - z11.d}, {z0.d - z3.d} // 11000001-11100001-01111001-00011010
+// CHECK-INST: sub za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x1a,0x79,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e1791a <unknown>
+
+sub za.d[w11, 2], {z8.d - z11.d}, {z0.d - z3.d} // 11000001-11100001-01111001-00011010
+// CHECK-INST: sub za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x1a,0x79,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e1791a <unknown>
+
+sub za.d[w9, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-00111001-10011111
+// CHECK-INST: sub za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x9f,0x39,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9399f <unknown>
+
+sub za.d[w9, 7], {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-00111001-10011111
+// CHECK-INST: sub za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x9f,0x39,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e9399f <unknown>
+
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