[PATCH] D129735: [WIP][RISCV] Add new pass to transform undef to zero-init for vector values.

[Piyou Chen via Phabricator via llvm-commits]

BeMg commandeered this revision.
BeMg added a reviewer: kito-cheng.
BeMg added a comment.

Here is a new approach that using the pseudo instruction to replace the undef value and remove it in later pass.

The way doesn't generate the extra instruction for initializing undef and let instruction maintain instruction early-clobber feature in RA stage.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735