[PATCH] D136051: [CodeGen] Introduce a flag to allow same cycle def-use schedule

[Suyog Sarda via Phabricator via llvm-commits]

ssarda added a comment.

Hi @bcahoon, i am yet to come across a case in Hexagon where in a linear list of instruction, a use occurs before def in orderDependence(). I assume, that's never a case for Hexagon happening yet. As pointed out by @dpenry, orderDependence() is not robust for other targets to make sure that def-use are in proper order, because of which we are trying to avoid same cycle scheduling by having check in isValidSchedule() function. But since, this is not the case with Hexagon target, this patch enables same cycle def-use scheduling for only Hexagon with a flag. Let us know your thoughts over it.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D136051/new/

https://reviews.llvm.org/D136051