[PATCH] D136264: [libunwind][RISCV] Support reading of VLENB CSR register

[Sergei Kachkov via Phabricator via llvm-commits]

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Support reading of VLENB (vector byte length) control register, that can be required for correct unwinding of RVV objects on stack.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136264

Files:
  libunwind/include/__libunwind_config.h
  libunwind/include/libunwind.h
  libunwind/src/Registers.hpp


Index: libunwind/src/Registers.hpp
===================================================================
--- libunwind/src/Registers.hpp
+++ libunwind/src/Registers.hpp
@@ -4084,6 +4084,8 @@
     return true;
   if (regNum < 0)
     return false;
+  if (regNum == UNW_RISCV_VLENB)
+    return true;
   if (regNum > UNW_RISCV_F31)
     return false;
   return true;
@@ -4098,6 +4100,11 @@
     return 0;
   if ((regNum > 0) && (regNum < 32))
     return _registers[regNum];
+  if (regNum == UNW_RISCV_VLENB) {
+    reg_t vlenb;
+    asm("csrr %0, 0xC22" : "=r"(vlenb) :);
+    return vlenb;
+  }
   _LIBUNWIND_ABORT("unsupported riscv register");
 }
 
@@ -4249,6 +4256,8 @@
     return "ft10";
   case UNW_RISCV_F31:
     return "ft11";
+  case UNW_RISCV_VLENB:
+    return "vlenb";
   default:
     return "unknown register";
   }
Index: libunwind/include/libunwind.h
===================================================================
--- libunwind/include/libunwind.h
+++ libunwind/include/libunwind.h
@@ -1023,6 +1023,7 @@
   UNW_RISCV_F29 = 61,
   UNW_RISCV_F30 = 62,
   UNW_RISCV_F31 = 63,
+  UNW_RISCV_VLENB = 0x1C22
 };
 
 // VE register numbers
Index: libunwind/include/__libunwind_config.h
===================================================================
--- libunwind/include/__libunwind_config.h
+++ libunwind/include/__libunwind_config.h
@@ -27,7 +27,7 @@
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC     31
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC64   31
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_HEXAGON   34
-#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV     64
+#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV     8191
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE        143
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_S390X     83
 


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