[PATCH] D136236: [AMDGPU][GISel] Allow VReg srcs in (build_vector undef, i16) pattern

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:2740-2741
 def : GCNPat <
-  (v2i16 (DivergentBinFrag<build_vector> (i16 undef), (i16 SReg_32:$src1))),
+  (v2i16 (DivergentBinFrag<build_vector> (i16 undef), (i16 VS_32:$src1))),
   (v2i16 (V_LSHLREV_B32_e64 (i32 16), SReg_32:$src1))
 >;
----------------
Why does this pattern use SReg_32? That doesn't make any sense to me.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136236/new/

https://reviews.llvm.org/D136236