[PATCH] D136236: [AMDGPU][GISel] Allow VReg srcs in (build_vector undef, i16) pattern

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh created this revision.
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Fixes a regression in v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt.

Depends on D134354 <https://reviews.llvm.org/D134354>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136236

Files:
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll


Index: llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
+++ llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
@@ -323,12 +323,12 @@
 }
 
 define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %src0, half %src1, half %src2) #0 {
-; DAG-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
-; DAG-GFX9:       ; %bb.0:
-; DAG-GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; DAG-GFX9-NEXT:    v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; DAG-GFX9-NEXT:    v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; DAG-GFX9-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT:    v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; DAG-VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
 ; DAG-VI:       ; %bb.0:
@@ -348,15 +348,6 @@
 ; DAG-CI-NEXT:    v_cvt_f32_f16_e32 v1, v0
 ; DAG-CI-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GISEL-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
-; GISEL-GFX9:       ; %bb.0:
-; GISEL-GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9-NEXT:    v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX9-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v0
-; GISEL-GFX9-NEXT:    v_lshl_or_b32 v0, v0, 16, v1
-; GISEL-GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
 ; GISEL-VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
 ; GISEL-VI:       ; %bb.0:
 ; GISEL-VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
Index: llvm/lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstructions.td
+++ llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2737,7 +2737,7 @@
 >;
 
 def : GCNPat <
-  (v2i16 (DivergentBinFrag<build_vector> (i16 undef), (i16 SReg_32:$src1))),
+  (v2i16 (DivergentBinFrag<build_vector> (i16 undef), (i16 VS_32:$src1))),
   (v2i16 (V_LSHLREV_B32_e64 (i32 16), SReg_32:$src1))
 >;
 
@@ -2748,7 +2748,7 @@
 >;
 
 def : GCNPat <
-  (v2f16 (DivergentBinFrag<build_vector> (f16 undef), (f16 SReg_32:$src1))),
+  (v2f16 (DivergentBinFrag<build_vector> (f16 undef), (f16 VS_32:$src1))),
   (v2f16 (V_LSHLREV_B32_e64 (i32 16), SReg_32:$src1))
 >;
 }


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