[PATCH] D136195: [AMDGPU] V_LDEXP_F16 encoding fix and doc update.

[Joe Nash via Phabricator via llvm-commits]

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The amdgcn.ldexp.* intrinsics take an i32 value as src1.
The V_LDEXP_F16 instruction considers src1 an f16 operand, and therefore
src1 is implicitly truncated to 16 bits when lowering to that instruction from the
intrinsic. This is unlikely to result in an error in practice
because values that large are not useful.

The operand class of src1 in the True16 version of the instruction has
been corrected to encode correctly on GFX11.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136195

Files:
  llvm/include/llvm/IR/IntrinsicsAMDGPU.td
  llvm/lib/Target/AMDGPU/VOP2Instructions.td
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ldexp.f16.ll
  llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
  llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s

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