[PATCH] D136152: [AMDGPU][MC][GFX8+] Correct v_cndmask operand types

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

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This is a follow up on https://reviews.llvm.org/D135900.
It turned out floating-point modifiers should be used with floating-point operands, otherwise an assert <https://github.com/llvm/llvm-project/blob/9e37301cf483237695325e199393ba5a84b7fc1e/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp#L2143> may be triggered. The issue manifests itself with e32 and sdwa variants, for example:

  v_cndmask_b32_e32 v5, |-4.0|, v2, vcc

The patch corrects operand types and adds more tests.


https://reviews.llvm.org/D136152

Files:
  llvm/lib/Target/AMDGPU/VOP2Instructions.td
  llvm/test/MC/AMDGPU/gfx10_asm_vop2.s


Index: llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
===================================================================
--- llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
+++ llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
@@ -35,6 +35,10 @@
 // W64: encoding: [0xf7,0x04,0x0a,0x02]
 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
+v_cndmask_b32_e32 v5, |-4.0|, v2, vcc
+// W64: encoding: [0xf6,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
 v_cndmask_b32_e32 v5, v1, v255, vcc
 // W64: encoding: [0x01,0xff,0x0b,0x02]
 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
@@ -115,6 +119,10 @@
 // W64: encoding: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x26,0x16]
 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
+v_cndmask_b32_sdwa v5, |0.5|, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x02,0xf0,0x06,0xa6,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
 v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 // W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x98,0x00]
 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
@@ -155,6 +163,10 @@
 // W32: encoding: [0xf7,0x04,0x0a,0x02]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
+v_cndmask_b32_e32 v5, |-4.0|, v2, vcc_lo
+// W32: encoding: [0xf6,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
 v_cndmask_b32_e32 v5, v1, v255, vcc_lo
 // W32: encoding: [0x01,0xff,0x0b,0x02]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
@@ -235,6 +247,10 @@
 // W32: encoding: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x26,0x16]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
+v_cndmask_b32_sdwa v5, |0.5|, -v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x02,0xf0,0x06,0xa6,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
 v_cndmask_b32_sdwa v5, sext(v1), v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 // W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand
Index: llvm/lib/Target/AMDGPU/VOP2Instructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -591,14 +591,14 @@
 
   // Suppress src2 implied by type since the 32-bit encoding uses an
   // implicit VCC use.
-  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
+  let Ins32 = (ins VSrc_f32:$src0, Src1RC32:$src1);
 
   let HasSrc0IntMods = 0;
   let HasSrc1IntMods = 0;
   let HasSrc0FloatMods = 1;
   let HasSrc1FloatMods = 1;
-  let InsSDWA = (ins FP32SDWAInputMods:$src0_modifiers, Src0SDWA:$src0,
-                     FP32SDWAInputMods:$src1_modifiers, Src1SDWA:$src1,
+  let InsSDWA = (ins FP32SDWAInputMods:$src0_modifiers, SDWASrc_f32:$src0,
+                     FP32SDWAInputMods:$src1_modifiers, SDWASrc_f32:$src1,
                      clampmod:$clamp,
                      dst_sel:$dst_sel, dst_unused:$dst_unused,
                      src0_sel:$src0_sel, src1_sel:$src1_sel);


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