[PATCH] D132196: [PowerPC] Add combine logic to use MADDLD/MADDHD/MADDHDU in multiply-add patterns

[Ting Wang via Phabricator via llvm-commits]

tingwang marked 2 inline comments as done.
tingwang added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:17179
+  // should have zero sign bit which map to unsigned, all others depend on
+  // SignBitIsZero.
+  auto IsLegalOperand = [&DAG](SDValue Op, unsigned &NumSignBits,
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shchenz wrote:
> `maddld` and `maddhd` are valid for 64 bit integers which include sign bit at the bit-0. So I think here we should expect there are at least 64 + 1= 65 sign bits?
> For the 64 sign bits and zero sign bit case, I guess the case is like: we have 0 in all the high 64 bits, and we have 1 in the first bit of the low 64 bits?(Otherwise, the sign bits number must be at least 65?) If so, this is not a case can be handled correctly either. We are expecting zero extension, but the low 64 bits value which can be accessed by maddld/maddhd is a signed value.
Thank you for pointing out. Updated accordingly.


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  https://reviews.llvm.org/D132196/new/

https://reviews.llvm.org/D132196