[PATCH] D132196: [PowerPC] Add combine logic to use MADDLD/MADDHD/MADDHDU in multiply-add patterns

[Ting Wang via Phabricator via llvm-commits]

tingwang updated this revision to Diff 468442.
tingwang added a comment.

Update according to comments:
(1) Drop sub patterns.
(2) Update check criteria to allow combined signed/unsigned operands as long as NumSignBits >= 65, and is served by madd[l/h]d.
(3) NumSignBits == 64 and SignBitIsZero is the only case served by maddhdu.

All IR test pattern results compared between P8 <https://reviews.llvm.org/P8> and P9 <https://reviews.llvm.org/P9> by attached script.
F24956723: madd_gen_test.pl <https://reviews.llvm.org/F24956723>


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132196/new/

https://reviews.llvm.org/D132196

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/test/CodeGen/PowerPC/add-int128-madd.ll
  llvm/test/CodeGen/PowerPC/mulld.ll

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