[llvm] 0c22f4f - [AMDGPU] Common up some generated checks in fnearbyint.ll
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 17 03:03:12 PDT 2022
Author: Jay Foad
Date: 2022-10-17T11:02:19+01:00
New Revision: 0c22f4f5fe44a9d3bb63d9cef699203c8da0a5d7
URL: https://github.com/llvm/llvm-project/commit/0c22f4f5fe44a9d3bb63d9cef699203c8da0a5d7
DIFF: https://github.com/llvm/llvm-project/commit/0c22f4f5fe44a9d3bb63d9cef699203c8da0a5d7.diff
LOG: [AMDGPU] Common up some generated checks in fnearbyint.ll
Also remove -mattr=-flat-for-global which is not needed for generated
checks.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/fnearbyint.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/fnearbyint.ll b/llvm/test/CodeGen/AMDGPU/fnearbyint.ll
index 52eb5ec6e5b62..24dc277c8e734 100644
--- a/llvm/test/CodeGen/AMDGPU/fnearbyint.ll
+++ b/llvm/test/CodeGen/AMDGPU/fnearbyint.ll
@@ -1,8 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=CI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
-
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=SICI,SI %s
+; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=SICI,CI %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
declare half @llvm.nearbyint.f16(half) #0
declare float @llvm.nearbyint.f32(float) #0
@@ -12,7 +11,6 @@ declare double @llvm.nearbyint.f64(double) #0
declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) #0
declare <4 x double> @llvm.nearbyint.v4f64(<4 x double>) #0
-
define amdgpu_kernel void @fnearbyint_f16(half addrspace(1)* %out, half %in) #1 {
; SI-LABEL: fnearbyint_f16:
; SI: ; %bb.0:
@@ -42,13 +40,13 @@ define amdgpu_kernel void @fnearbyint_f16(half addrspace(1)* %out, half %in) #1
;
; VI-LABEL: fnearbyint_f16:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s4, s[0:1], 0x2c
+; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s3, 0xf000
-; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_rndne_f16_e32 v0, s4
-; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
+; VI-NEXT: v_rndne_f16_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
%1 = call half @llvm.nearbyint.f16(half %in)
store half %1, half addrspace(1)* %out
@@ -56,37 +54,26 @@ define amdgpu_kernel void @fnearbyint_f16(half addrspace(1)* %out, half %in) #1
}
define amdgpu_kernel void @fnearbyint_f32(float addrspace(1)* %out, float %in) #1 {
-; SI-LABEL: fnearbyint_f32:
-; SI: ; %bb.0: ; %entry
-; SI-NEXT: s_load_dword s4, s[0:1], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_rndne_f32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; CI-LABEL: fnearbyint_f32:
-; CI: ; %bb.0: ; %entry
-; CI-NEXT: s_load_dword s4, s[0:1], 0xb
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; CI-NEXT: s_mov_b32 s3, 0xf000
-; CI-NEXT: s_mov_b32 s2, -1
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_rndne_f32_e32 v0, s4
-; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; CI-NEXT: s_endpgm
+; SICI-LABEL: fnearbyint_f32:
+; SICI: ; %bb.0: ; %entry
+; SICI-NEXT: s_load_dword s4, s[0:1], 0xb
+; SICI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SICI-NEXT: s_mov_b32 s3, 0xf000
+; SICI-NEXT: s_mov_b32 s2, -1
+; SICI-NEXT: s_waitcnt lgkmcnt(0)
+; SICI-NEXT: v_rndne_f32_e32 v0, s4
+; SICI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SICI-NEXT: s_endpgm
;
; VI-LABEL: fnearbyint_f32:
; VI: ; %bb.0: ; %entry
-; VI-NEXT: s_load_dword s4, s[0:1], 0x2c
+; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s3, 0xf000
-; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_rndne_f32_e32 v0, s4
-; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: v_rndne_f32_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
entry:
%0 = call float @llvm.nearbyint.f32(float %in)
@@ -95,43 +82,28 @@ entry:
}
define amdgpu_kernel void @fnearbyint_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) #1 {
-; SI-LABEL: fnearbyint_v2f32:
-; SI: ; %bb.0: ; %entry
-; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, s0
-; SI-NEXT: s_mov_b32 s5, s1
-; SI-NEXT: v_rndne_f32_e32 v1, s3
-; SI-NEXT: v_rndne_f32_e32 v0, s2
-; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; SI-NEXT: s_endpgm
-;
-; CI-LABEL: fnearbyint_v2f32:
-; CI: ; %bb.0: ; %entry
-; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
-; CI-NEXT: s_mov_b32 s7, 0xf000
-; CI-NEXT: s_mov_b32 s6, -1
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: s_mov_b32 s4, s0
-; CI-NEXT: s_mov_b32 s5, s1
-; CI-NEXT: v_rndne_f32_e32 v1, s3
-; CI-NEXT: v_rndne_f32_e32 v0, s2
-; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; CI-NEXT: s_endpgm
+; SICI-LABEL: fnearbyint_v2f32:
+; SICI: ; %bb.0: ; %entry
+; SICI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SICI-NEXT: s_mov_b32 s7, 0xf000
+; SICI-NEXT: s_mov_b32 s6, -1
+; SICI-NEXT: s_waitcnt lgkmcnt(0)
+; SICI-NEXT: s_mov_b32 s4, s0
+; SICI-NEXT: s_mov_b32 s5, s1
+; SICI-NEXT: v_rndne_f32_e32 v1, s3
+; SICI-NEXT: v_rndne_f32_e32 v0, s2
+; SICI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SICI-NEXT: s_endpgm
;
; VI-LABEL: fnearbyint_v2f32:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s7, 0xf000
-; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, s0
-; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_rndne_f32_e32 v1, s3
; VI-NEXT: v_rndne_f32_e32 v0, s2
-; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
entry:
%0 = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %in)
@@ -140,46 +112,32 @@ entry:
}
define amdgpu_kernel void @fnearbyint_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) #1 {
-; SI-LABEL: fnearbyint_v4f32:
-; SI: ; %bb.0: ; %entry
-; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
-; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_rndne_f32_e32 v3, s7
-; SI-NEXT: v_rndne_f32_e32 v2, s6
-; SI-NEXT: v_rndne_f32_e32 v1, s5
-; SI-NEXT: v_rndne_f32_e32 v0, s4
-; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; CI-LABEL: fnearbyint_v4f32:
-; CI: ; %bb.0: ; %entry
-; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; CI-NEXT: s_mov_b32 s3, 0xf000
-; CI-NEXT: s_mov_b32 s2, -1
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_rndne_f32_e32 v3, s7
-; CI-NEXT: v_rndne_f32_e32 v2, s6
-; CI-NEXT: v_rndne_f32_e32 v1, s5
-; CI-NEXT: v_rndne_f32_e32 v0, s4
-; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
-; CI-NEXT: s_endpgm
+; SICI-LABEL: fnearbyint_v4f32:
+; SICI: ; %bb.0: ; %entry
+; SICI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
+; SICI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SICI-NEXT: s_mov_b32 s3, 0xf000
+; SICI-NEXT: s_mov_b32 s2, -1
+; SICI-NEXT: s_waitcnt lgkmcnt(0)
+; SICI-NEXT: v_rndne_f32_e32 v3, s7
+; SICI-NEXT: v_rndne_f32_e32 v2, s6
+; SICI-NEXT: v_rndne_f32_e32 v1, s5
+; SICI-NEXT: v_rndne_f32_e32 v0, s4
+; SICI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SICI-NEXT: s_endpgm
;
; VI-LABEL: fnearbyint_v4f32:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s3, 0xf000
-; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_rndne_f32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_rndne_f32_e32 v2, s6
; VI-NEXT: v_rndne_f32_e32 v1, s5
; VI-NEXT: v_rndne_f32_e32 v0, s4
-; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; VI-NEXT: v_mov_b32_e32 v4, s0
+; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
entry:
%0 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %in)
@@ -228,9 +186,9 @@ define amdgpu_kernel void @nearbyint_f64(double addrspace(1)* %out, double %in)
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_rndne_f64_e32 v[0:1], s[2:3]
-; VI-NEXT: s_mov_b32 s3, 0xf000
-; VI-NEXT: s_mov_b32 s2, -1
-; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
entry:
%0 = call double @llvm.nearbyint.f64(double %in)
@@ -289,12 +247,12 @@ define amdgpu_kernel void @nearbyint_v2f64(<2 x double> addrspace(1)* %out, <2 x
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s3, 0xf000
-; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_rndne_f64_e32 v[2:3], s[6:7]
; VI-NEXT: v_rndne_f64_e32 v[0:1], s[4:5]
-; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; VI-NEXT: v_mov_b32_e32 v5, s1
+; VI-NEXT: v_mov_b32_e32 v4, s0
+; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
entry:
%0 = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %in)
@@ -376,15 +334,19 @@ define amdgpu_kernel void @nearbyint_v4f64(<4 x double> addrspace(1)* %out, <4 x
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x44
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT: s_mov_b32 s3, 0xf000
-; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_rndne_f64_e32 v[6:7], s[10:11]
; VI-NEXT: v_rndne_f64_e32 v[4:5], s[8:9]
; VI-NEXT: v_rndne_f64_e32 v[2:3], s[6:7]
; VI-NEXT: v_rndne_f64_e32 v[0:1], s[4:5]
-; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
-; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; VI-NEXT: s_add_u32 s2, s0, 16
+; VI-NEXT: s_addc_u32 s3, s1, 0
+; VI-NEXT: v_mov_b32_e32 v11, s3
+; VI-NEXT: v_mov_b32_e32 v9, s1
+; VI-NEXT: v_mov_b32_e32 v10, s2
+; VI-NEXT: v_mov_b32_e32 v8, s0
+; VI-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
+; VI-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; VI-NEXT: s_endpgm
entry:
%0 = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %in)
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