[PATCH] D136046: [X86] `DAGTypeLegalizer::ModifyToType()`: when widening w/ zeros, insert into undef and `and`-mask the padding away

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:7065
+  for (; Idx < WidenNumElts; ++Idx)
+    MaskOps[Idx] = ZeroVal;
+
----------------
Why not use append?
```
  SmallVector<SDValue, 16> MaskOps;
  MaskOps.append(MinNumElts, DAG.getAllOnesConstant(dl, EltVT));
  MaskOps.append(WidenNumElts - MinNumElts, DAG.getConstant(0, dl, EltVT));
```


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:7068
+  return DAG.getNode(ISD::AND, dl, NVT,
+                     {Widened, DAG.getBuildVector(NVT, dl, MaskOps)});
 }
----------------
why the braces?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D136046/new/

https://reviews.llvm.org/D136046