[PATCH] D136014: [AArch64] Improve codegen for shifted mask op

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14387
+  // The special case is ((x >> C) & mask) << C.
+  // It can be combine to x & (mask << C) by return true
   if (ShiftLHS.getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
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Allen wrote:
> Does it right when **(mask << C)** overflow ?
Yes, this patch only change if we can change the sequence of shift and binop(and, or, add).
Overflow logic should not have any difference.



CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136014/new/

https://reviews.llvm.org/D136014