[PATCH] D136014: [AArch64] Improve codegen for shifted mask op
Allen zhong via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 15 07:35:23 PDT 2022
Allen added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14387
+ // The special case is ((x >> C) & mask) << C.
+ // It can be combine to x & (mask << C) by return true
if (ShiftLHS.getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
----------------
Does it right when **(mask << C)** overflow ?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D136014/new/
https://reviews.llvm.org/D136014
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