[PATCH] D135869: [AMDGPU][DAG] Only apply trunc/shift combine to 16 bit types

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

> The shift amount check seems to be wrong. I think the correct condition is ShiftAmt <= (32 - VT.getScalarSizeInBits()) https://alive2.llvm.org/ce/z/uYZ9tq

For right shifts. For left shifts it's size.

GlobalISel also seems to have half ported this combine. For some reason it's only handling shl


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https://reviews.llvm.org/D135869