[PATCH] D135137: [AggressiveInstCombine] Load merge the reverse load pattern and mixed load sizes.

[Biplob Mishra via Phabricator via llvm-commits]

bipmis added a comment.

In D135137#3856034 <https://reviews.llvm.org/D135137#3856034>, @spatel wrote:

> This improves the pattern-matching, but it's still not complete, right? Ie, we should have a PhaseOrdering test with all 24 (4!) combinations of four i8-loads spliced into a 32-bit value, so we know the pattern is matched no matter what order the values are put back together with 'or'. We can probably rely on instcombine to canonicalize half of those patterns, but I'm not sure there's anything else there to reduce the matching space.

Right but won't these cover the most commonly seen patterns in the real application scenario, if not all considering it belongs to a pattern which generates a wider load.
InstCombine can possibly canonicalize the or-chain of loads in an ascending/descending order of load indexes. The fact that it is called multiple times should get us the pattern expected by AggressiveInstCombine. However, I am not sure if this is the right thing to do.


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https://reviews.llvm.org/D135137