[PATCH] D135952: [AArch64]Change printVectorList to print SVE vector range

[Caroline via Phabricator via llvm-commits]

CarolineConcatto created this revision.
Herald added subscribers: ctetreau, gbedwell, hiraditya, kristof.beyls, tschuett.
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CarolineConcatto requested review of this revision.
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This patch has the prefered disassembly changed for SVE vector list.
For instance, instead of printing this assembly:

  ld4d { z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]

it will print this:

  ld4d { z1.d-z4.d }, p0/z, [x0]


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135952

Files:
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
  llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
  llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+imm-addr-mode.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+reg-addr-mode.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-reg-addr-mode.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
  llvm/test/CodeGen/AArch64/sve-ldN.mir
  llvm/test/CodeGen/AArch64/sve-merging-stores.ll
  llvm/test/CodeGen/AArch64/sve-stN.mir
  llvm/test/CodeGen/AArch64/sve2-intrinsics-perm-tb.ll
  llvm/test/MC/AArch64/SVE/ld2b.s
  llvm/test/MC/AArch64/SVE/ld2d.s
  llvm/test/MC/AArch64/SVE/ld2h.s
  llvm/test/MC/AArch64/SVE/ld2w.s
  llvm/test/MC/AArch64/SVE/ld3b.s
  llvm/test/MC/AArch64/SVE/ld3d.s
  llvm/test/MC/AArch64/SVE/ld3h.s
  llvm/test/MC/AArch64/SVE/ld3w.s
  llvm/test/MC/AArch64/SVE/ld4b.s
  llvm/test/MC/AArch64/SVE/ld4d.s
  llvm/test/MC/AArch64/SVE/ld4h.s
  llvm/test/MC/AArch64/SVE/ld4w.s
  llvm/test/MC/AArch64/SVE/st2b.s
  llvm/test/MC/AArch64/SVE/st2d.s
  llvm/test/MC/AArch64/SVE/st2h.s
  llvm/test/MC/AArch64/SVE/st2w.s
  llvm/test/MC/AArch64/SVE/st3b.s
  llvm/test/MC/AArch64/SVE/st3d.s
  llvm/test/MC/AArch64/SVE/st3h.s
  llvm/test/MC/AArch64/SVE/st3w.s
  llvm/test/MC/AArch64/SVE/st4b.s
  llvm/test/MC/AArch64/SVE/st4d.s
  llvm/test/MC/AArch64/SVE/st4h.s
  llvm/test/MC/AArch64/SVE/st4w.s
  llvm/test/MC/AArch64/SVE2/ext.s
  llvm/test/MC/AArch64/SVE2/splice.s
  llvm/test/MC/AArch64/SVE2/tbl.s
  llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-sve-instructions.s
  llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s

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