[PATCH] D134277: [RISCV] Combine comparison and logic ops.
Ilya Andreev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 13 08:19:52 PDT 2022
iabg-sc updated this revision to Diff 467480.
iabg-sc added a comment.
Comparison operations are checked via bit fields.
SDNodes were removed. Now all actions only on SDValues.
Some cosmetic changes.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D134277/new/
https://reviews.llvm.org/D134277
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll
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