[PATCH] D134277: [RISCV] Combine comparison and logic ops.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll:11
 
 ; 4 patterns bellow will be converted to umin+less.
 define i1 @ulo(i64 %c, i64 %a, i64 %b) {
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below is misspelled


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  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D134277/new/

https://reviews.llvm.org/D134277