[PATCH] D135807: [WIP][RISCV][InsertVSETVLI] Allow promotion of TA to TU and MA to MU

Wed Oct 12 14:05:23 PDT 2022

craig.topper added inline comments.

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Comment at: llvm/test/CodeGen/RISCV/rvv/vmacc.ll:1572
+; RV32-NEXT:    vsetvli zero, a2, e64, m1, tu, ma
 ; RV32-NEXT:    vlse64.v v10, (a0), zero
 ; RV32-NEXT:    vmacc.vv v8, v10, v9
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reames wrote:
> craig.topper wrote:
> > If this were in a loop and a load misses the cache, the later iterations couldn't speculatively start loading until the earlier cache miss is resolved.  That doesn't seem ideal.
> Depends on how the hardware handles this, and I don't really know what's realistic.  In theory, the load can be issued, and only the merge is bottlenecked by the false dependency .  Not sure if that's a realistic hardware expectation or not.
> 
> Note that the vmacc has the same loop carried false dependency issue in either case.  So we're really just talking about the issue to overlap the loads.
> 
> But yes, unless the hardware is pretty uniformly smart about this - as sketched above - this would seem to be a fatal flaw for this patch.  
I guess on most of the loop iterations of the loop you would be using vlmax so there isn't a tail. So maybe only the last iteration would be affected.

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  https://reviews.llvm.org/D135807/new/

https://reviews.llvm.org/D135807