[PATCH] D135807: [WIP][RISCV][InsertVSETVLI] Allow promotion of TA to TU and MA to MU

Philip Reames via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Oct 12 13:41:05 PDT 2022


reames added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vmacc.ll:1572
+; RV32-NEXT:    vsetvli zero, a2, e64, m1, tu, ma
 ; RV32-NEXT:    vlse64.v v10, (a0), zero
 ; RV32-NEXT:    vmacc.vv v8, v10, v9
----------------
craig.topper wrote:
> If this were in a loop and a load misses the cache, the later iterations couldn't speculatively start loading until the earlier cache miss is resolved.  That doesn't seem ideal.
Depends on how the hardware handles this, and I don't really know what's realistic.  In theory, the load can be issued, and only the merge is bottlenecked by the false dependency .  Not sure if that's a realistic hardware expectation or not.

Note that the vmacc has the same loop carried false dependency issue in either case.  So we're really just talking about the issue to overlap the loads.

But yes, unless the hardware is pretty uniformly smart about this - as sketched above - this would seem to be a fatal flaw for this patch.  


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https://reviews.llvm.org/D135807



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