[PATCH] D135600: [RISCV] Use branchless form for selects with 0 in either arm

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/double-convert.ll:97
+; CHECKIFD-NEXT:    feq.d a1, fa0, fa0
+; CHECKIFD-NEXT:    seqz a1, a1
+; CHECKIFD-NEXT:    addi a1, a1, -1
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This is interesting. The seqz isn't necessary. I'll take a look at this.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135600/new/

https://reviews.llvm.org/D135600