[PATCH] D129735: [WIP][RISCV] Add new pass to transform undef to zero-init for vector values.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

In D129735#3848689 <https://reviews.llvm.org/D129735#3848689>, @rogfer01 wrote:

> At risk of introducing noise: would it make sense to use some pseudo instruction (e.g. `RISCV::PseudoVUNDEF_Mx`) instead of the zero initializations and then drop it later (say when emitting MCInst)?

@rogfer01, thanks for your suggestion, currently we have another colleague in SiFive is exploring different approach for this issue, and forwarded your suggestion to him :)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735