[PATCH] D135600: [RISCV] Use branchless form for selects with 0 in either arm

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9505
+    // (select c, y, 0) -> -c & y
+    if (isAllOnesConstant(FalseV)) {
+      SDValue C = DAG.getSetCC(DL, VT, LHS, RHS, CCVal);
----------------
craig.topper wrote:
> Too much copy/paste. :) This should be `isNullConstant`
Eek, how did I miss that?  I swear I looked at the test diffs too!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135600/new/

https://reviews.llvm.org/D135600