[PATCH] D135600: [RISCV] Use branchless form for selects with 0 in either arm

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9505
+    // (select c, y, 0) -> -c & y
+    if (isAllOnesConstant(FalseV)) {
+      SDValue C = DAG.getSetCC(DL, VT, LHS, RHS, CCVal);
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Too much copy/paste. :) This should be `isNullConstant`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135600/new/

https://reviews.llvm.org/D135600