[PATCH] D135538: [RISCV] Use hasAllWUsers to recover XORI/ORI

Sun Oct 9 22:54:47 PDT 2022

liaolucy added inline comments.

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Comment at: llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll:125
+; CHECK-NEXT:    subw a0, a0, a1
+; CHECK-NEXT:    addiw a0, a0, -8
+; CHECK-NEXT:    sw a0, 0(a2)
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craig.topper wrote:
> craig.topper wrote:
> > liaolucy wrote:
> > > looks good, no need to optimize.
> > The ADDI being before the SUBW probably means this didn’t test what it was supposed to.
> I attempted to make ADDI file but I haven't been able to.

https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp#L2597 add and sub use SimplifyDemandedBits.

Step4 of ISel: Optimized type-legalized selection DAG use SimplifyDemandedBits.

For addi:
Step2 of ISel: Optimized lowered selection DAG put the ADD before the SUB.  So it doesn't trigger

Actually, I was just thinking about deleting the test

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135538/new/

https://reviews.llvm.org/D135538