[PATCH] D135208: [AArch64] Swap 'lsl(val1, small-shmt)' to right hand side for ADD(lsl(val1,small-shmt), lsl(val2,large-shmt))

[Mingming Liu via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG159fb378f779: [AArch64] Swap 'lsl(val1,small-shmt)' to right hand side for AND(lsl(val1,small… (authored by mingmingl).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135208/new/

https://reviews.llvm.org/D135208

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/logical_shifted_reg.ll

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