[PATCH] D135208: [AArch64] Swap 'lsl(val1, small-shmt)' to right hand side for ADD(lsl(val1,small-shmt), lsl(val2,large-shmt))
Mingming Liu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 9 17:25:30 PDT 2022
mingmingl updated this revision to Diff 466402.
mingmingl added a comment.
Fix the typo (ADDD -> ADD)
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D135208/new/
https://reviews.llvm.org/D135208
Files:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
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