[PATCH] D135538: [RISCV] Use hasAllWUsers to recover XORI/ORI

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Oct 9 10:08:58 PDT 2022


craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll:125
+; CHECK-NEXT:    subw a0, a0, a1
+; CHECK-NEXT:    addiw a0, a0, -8
+; CHECK-NEXT:    sw a0, 0(a2)
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liaolucy wrote:
> looks good, no need to optimize.
The ADDI being before the SUBW probably means this didn’t test what it was supposed to.


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Comment at: llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll:159
+}
 ; SimplifyDemandedBits breaks the ANDI by turning -8 into 0xfffffff8. This
 ; gets CSEd with the AND needed for type legalizing the lshr. This increases
----------------
Add blank line


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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135538/new/

https://reviews.llvm.org/D135538



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