[PATCH] D135514: Add isel pattern for (setne/eq (sext_inreg GPR), 0) to remove sext_inreg

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy created this revision.
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Spec:
SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, 
otherwise sets rd to zero (assembler pseudoinstruction SNEZ rd, rs).

SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals zero, 
otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs).

(setne/eq (sext_inreg GPR:$rs), 0) only check if rs is 0. 
If rs is 0, sext_inreg rs is also 0.
If rs is not 0, sext_inreg rs is not 0.

So the sext_inreg is redundant.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135514

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/aext-to-sext.ll
  llvm/test/CodeGen/RISCV/i64-icmp.ll
  llvm/test/CodeGen/RISCV/setcc-logic.ll
  llvm/test/CodeGen/RISCV/xaluo.ll


Index: llvm/test/CodeGen/RISCV/xaluo.ll
===================================================================
--- llvm/test/CodeGen/RISCV/xaluo.ll
+++ llvm/test/CodeGen/RISCV/xaluo.ll
@@ -434,7 +434,7 @@
 ;
 ; RV64-LABEL: uaddo.i32.constant_one:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    addiw a2, a0, 1
+; RV64-NEXT:    addi a2, a0, 1
 ; RV64-NEXT:    seqz a0, a2
 ; RV64-NEXT:    sw a2, 0(a1)
 ; RV64-NEXT:    ret
@@ -448,7 +448,7 @@
 ;
 ; RV64ZBA-LABEL: uaddo.i32.constant_one:
 ; RV64ZBA:       # %bb.0: # %entry
-; RV64ZBA-NEXT:    addiw a2, a0, 1
+; RV64ZBA-NEXT:    addi a2, a0, 1
 ; RV64ZBA-NEXT:    seqz a0, a2
 ; RV64ZBA-NEXT:    sw a2, 0(a1)
 ; RV64ZBA-NEXT:    ret
Index: llvm/test/CodeGen/RISCV/setcc-logic.ll
===================================================================
--- llvm/test/CodeGen/RISCV/setcc-logic.ll
+++ llvm/test/CodeGen/RISCV/setcc-logic.ll
@@ -18,7 +18,6 @@
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    xor a1, a2, a3
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    ret
   %cmp1 = icmp eq i32 %a, %b
@@ -41,7 +40,6 @@
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    xor a1, a2, a3
 ; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    ret
   %cmp1 = icmp ne i32 %a, %b
Index: llvm/test/CodeGen/RISCV/i64-icmp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/i64-icmp.ll
+++ llvm/test/CodeGen/RISCV/i64-icmp.ll
@@ -725,7 +725,6 @@
 define i64 @icmp_ne_zext_inreg_small_constant(i64 %a) nounwind {
 ; RV64I-LABEL: icmp_ne_zext_inreg_small_constant:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    ret
   %1 = and i64 %a, 4294967295
Index: llvm/test/CodeGen/RISCV/aext-to-sext.ll
===================================================================
--- llvm/test/CodeGen/RISCV/aext-to-sext.ll
+++ llvm/test/CodeGen/RISCV/aext-to-sext.ll
@@ -54,7 +54,6 @@
 define i32 @crash(i32 %x, i32 %y, i32 %z) {
 ; RV64I-LABEL: crash:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    seqz a3, a0
 ; RV64I-NEXT:    addw a0, a1, a2
 ; RV64I-NEXT:    slli a1, a3, 3
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1287,12 +1287,14 @@
 // Define pattern expansions for setcc operations that aren't directly
 // handled by a RISC-V instruction.
 def : Pat<(seteq GPR:$rs1, 0), (SLTIU GPR:$rs1, 1)>;
+def : Pat<(seteq (sext_inreg GPR:$rs1, i32), 0), (SLTIU GPR:$rs1, 1)>;
 def : Pat<(seteq GPR:$rs1, GPR:$rs2), (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>;
 def : Pat<(seteq GPR:$rs1, simm12_plus1:$imm12),
           (SLTIU (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)), 1)>;
 def : Pat<(seteq GPR:$rs1, -2048),
           (SLTIU (XORI GPR:$rs1, -2048), 1)>;
 def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>;
+def : Pat<(setne (sext_inreg GPR:$rs1, i32), 0), (SLTU X0, GPR:$rs1)>;
 def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>;
 def : Pat<(setne GPR:$rs1, simm12_plus1:$imm12),
           (SLTU X0, (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)))>;


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