[llvm] 62ea6c5 - [DAGCombine] Deduplicate addcarry node using commutativity.

[Paweł Bylica via llvm-commits]

Author: Amaury Séchet
Date: 2022-10-08T00:55:14+02:00
New Revision: 62ea6c5be785ff149fa593b431b4d5053e2b81a8

URL: https://github.com/llvm/llvm-project/commit/62ea6c5be785ff149fa593b431b4d5053e2b81a8
DIFF: https://github.com/llvm/llvm-project/commit/62ea6c5be785ff149fa593b431b4d5053e2b81a8.diff

LOG: [DAGCombine] Deduplicate addcarry node using commutativity.

The first two parameters of addcarry are commutative. We may face a situation where both variant are present in the DAG, in which case we benefit from using just one.

Depends on D57302 and D33587

Reviewed By: RKSimon, chfast

Differential Revision: https://reviews.llvm.org/D57317

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/test/CodeGen/X86/addcarry.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index eb69a07b96adb..195238eda3b92 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3061,6 +3061,17 @@ SDValue DAGCombiner::visitADDCARRY(SDNode *N) {
   if (SDValue Combined = visitADDCARRYLike(N1, N0, CarryIn, N))
     return Combined;
 
+  // We want to avoid useless duplication.
+  // TODO: This is done automatically for binary operations. As ADDCARRY is
+  // not a binary operation, this is not really possible to leverage this
+  // existing mechanism for it. However, if more operations require the same
+  // deduplication logic, then it may be worth generalize.
+  SDValue Ops[] = {N1, N0, CarryIn};
+  SDNode *CSENode =
+      DAG.getNodeIfExists(ISD::ADDCARRY, N->getVTList(), Ops, N->getFlags());
+  if (CSENode)
+    return SDValue(CSENode, 0);
+
   return SDValue();
 }
 

diff  --git a/llvm/test/CodeGen/X86/addcarry.ll b/llvm/test/CodeGen/X86/addcarry.ll
index c95525f687cce..95ee94551a7e5 100644
--- a/llvm/test/CodeGen/X86/addcarry.ll
+++ b/llvm/test/CodeGen/X86/addcarry.ll
@@ -1397,13 +1397,10 @@ define i32 @addcarry_uge(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
 define { i64, i64 } @addcarry_commutative_1(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind {
 ; CHECK-LABEL: addcarry_commutative_1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    addq %rdx, %rax
 ; CHECK-NEXT:    movq %rsi, %rax
-; CHECK-NEXT:    adcq %rcx, %rax
 ; CHECK-NEXT:    addq %rdx, %rdi
-; CHECK-NEXT:    adcq %rcx, %rsi
-; CHECK-NEXT:    movq %rsi, %rdx
+; CHECK-NEXT:    adcq %rcx, %rax
+; CHECK-NEXT:    movq %rax, %rdx
 ; CHECK-NEXT:    retq
   %z0 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x0, i64 %y0)
   %k0 = extractvalue { i64, i1 } %z0, 1
@@ -1424,13 +1421,10 @@ define { i64, i64 } @addcarry_commutative_1(i64 %x0, i64 %x1, i64 %y0, i64 %y1)
 define { i64, i64 } @addcarry_commutative_2(i64 %x0, i64 %x1, i64 %y0, i64 %y1) nounwind {
 ; CHECK-LABEL: addcarry_commutative_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    addq %rdx, %rax
 ; CHECK-NEXT:    movq %rsi, %rax
-; CHECK-NEXT:    adcq %rcx, %rax
 ; CHECK-NEXT:    addq %rdx, %rdi
-; CHECK-NEXT:    adcq %rcx, %rsi
-; CHECK-NEXT:    movq %rsi, %rdx
+; CHECK-NEXT:    adcq %rcx, %rax
+; CHECK-NEXT:    movq %rax, %rdx
 ; CHECK-NEXT:    retq
   %z0 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x0, i64 %y0)
   %k0 = extractvalue { i64, i1 } %z0, 1