[llvm] 42cb2f8 - [GlobalISel] Mark mi_match as nodiscard

[Jessica Paquette via llvm-commits]

Author: Jessica Paquette
Date: 2022-10-07T15:47:05-07:00
New Revision: 42cb2f8b1298835575a839e184d738086c22c766

URL: https://github.com/llvm/llvm-project/commit/42cb2f8b1298835575a839e184d738086c22c766
DIFF: https://github.com/llvm/llvm-project/commit/42cb2f8b1298835575a839e184d738086c22c766.diff

LOG: [GlobalISel] Mark mi_match as nodiscard

Typically when you match something, you want to check the result.

Fix a couple warnings in the AMDGPUPostLegalizerCombiner which appear as a
result of this.

Differential Revision: https://reviews.llvm.org/D135491

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
    llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

Removed: 
    


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diff  --git a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
index b1795aa429e9c..91216cfc489e7 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
@@ -22,12 +22,14 @@ namespace llvm {
 namespace MIPatternMatch {
 
 template <typename Reg, typename Pattern>
-bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P) {
+[[nodiscard]] bool mi_match(Reg R, const MachineRegisterInfo &MRI,
+                            Pattern &&P) {
   return P.match(MRI, R);
 }
 
 template <typename Pattern>
-bool mi_match(MachineInstr &MI, const MachineRegisterInfo &MRI, Pattern &&P) {
+[[nodiscard]] bool mi_match(MachineInstr &MI, const MachineRegisterInfo &MRI,
+                            Pattern &&P) {
   return P.match(MRI, &MI);
 }
 

diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
index 17006030089e6..3dccb616b79c9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
@@ -221,7 +221,9 @@ bool AMDGPUPostLegalizerCombinerHelper::matchRcpSqrtToRsq(
 
   auto getSqrtSrc = [=](const MachineInstr &MI) {
     MachineInstr *SqrtSrcMI = nullptr;
-    mi_match(MI.getOperand(0).getReg(), MRI, m_GFSqrt(m_MInstr(SqrtSrcMI)));
+    auto Match =
+        mi_match(MI.getOperand(0).getReg(), MRI, m_GFSqrt(m_MInstr(SqrtSrcMI)));
+    (void)Match;
     return SqrtSrcMI;
   };
 
@@ -254,11 +256,11 @@ bool AMDGPUPostLegalizerCombinerHelper::matchCvtF32UByteN(
   Register SrcReg = MI.getOperand(1).getReg();
 
   // Look through G_ZEXT.
-  mi_match(SrcReg, MRI, m_GZExt(m_Reg(SrcReg)));
+  bool IsShr = mi_match(SrcReg, MRI, m_GZExt(m_Reg(SrcReg)));
 
   Register Src0;
   int64_t ShiftAmt;
-  bool IsShr = mi_match(SrcReg, MRI, m_GLShr(m_Reg(Src0), m_ICst(ShiftAmt)));
+  IsShr = mi_match(SrcReg, MRI, m_GLShr(m_Reg(Src0), m_ICst(ShiftAmt)));
   if (IsShr || mi_match(SrcReg, MRI, m_GShl(m_Reg(Src0), m_ICst(ShiftAmt)))) {
     const unsigned Offset = MI.getOpcode() - AMDGPU::G_AMDGPU_CVT_F32_UBYTE0;