[PATCH] D135396: [RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 6 13:40:42 PDT 2022 

craig.topper created this revision.
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If the source is implicit_def, the register allocator won't have
any constraint on what register it picks for the destination. This
doesn't give the user much control of what register is being used.

So in my mind that means the only reason to honor the policy operand
is to control what policy is used in vsetvli to maybe avoid a vtype
change. Given the other optimizations we do on the policy field, I
don't think allowing the user this control is reliable.

Therefore, I think we should use agnostic policies if the source is
undef.

This should give better performance on some CPUs for VP intrinsics where
there is no merge operand and the backend adds IMPLICIT_DEF to the instruction.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135396

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
  llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-fpext-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
  llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll
  llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
  llvm/test/CodeGen/RISCV/rvv/round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
  llvm/test/CodeGen/RISCV/rvv/strided-load-store-intrinsics.ll
  llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vpload.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll

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