[PATCH] D135324: [AArch64-SVE]: force using SVE in streaming mode to lower arithmetic and logical fixed-width vector ops.

[Hassnaa Hamdi via Phabricator via llvm-commits]

hassnaa-arm added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll:8
 
-define <8 x i16> @load_zext_v8i8i16(<8 x i8>* %ap)  #0 {
-; CHECK-LABEL: load_zext_v8i8i16:
+define <8 x i16> @load_zext_v16i8i32(<8 x i8>* %ap)  #0 {
+; CHECK-LABEL: load_zext_v16i8i32:
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david-arm wrote:
> I don't think these changes should be part of this patch, since it's not changing loads and stores?
I'm sorry, it's by mistake.
I will correct it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135324/new/

https://reviews.llvm.org/D135324