[PATCH] D135102: [AArch64] Combine or(and(val,shifted-mask), op) to or(shl(and(srl(val,N), mask), N), op)

Mingming Liu via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 4 00:15:42 PDT 2022


mingmingl updated this revision to Diff 464896.
mingmingl retitled this revision from "[AArch64] Combine or(and(val,shifted-mask), op) to or(shl(and(val>>N, mask), N), op)" to "[AArch64] Combine or(and(val,shifted-mask), op) to or(shl(and(srl(val,N), mask), N), op)".
mingmingl edited the summary of this revision.
mingmingl added a comment.

Fix code style issues (nested if, etc)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135102/new/

https://reviews.llvm.org/D135102

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-lsr-bfi.ll
  llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
  llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-innerouter.ll

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