[PATCH] D134703: [RISCV][ISel] Refactor the formation of VW operations

[Quentin Colombet via Phabricator via llvm-commits]

qcolombet added a comment.

> I've reversed the parent/child links so that the patches that need to come first are parents and the later patches are children.

Oh thanks!
Stupid me!!



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8217
+    SDLoc DL(Root);
+    std::pair<SDValue, SDValue> MaskAndVL = getMaskAndVL(Root);
+    switch (OrigOperand.getOpcode()) {
----------------
craig.topper wrote:
> I think using `auto [Mask, VL] = getMaskAndVL(Root);` would be consistent with D134442.
Sounds good to me.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8271
+    default:
+      llvm_unreachable("Unepexted opcode");
+    }
----------------
craig.topper wrote:
> Unexpected*
Good catch!


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8369
+  static bool isSupportedRoot(const SDNode *Root) {
+    if (!Root)
+      return false;
----------------
craig.topper wrote:
> Would `Root` ever be null?
Technically no.
We can get rid of the check.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D134703/new/

https://reviews.llvm.org/D134703