[PATCH] D131389: [AArch64] Add Missing v8.8a ALLINT PSTATE

Sam Elliott via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 29 06:08:24 PDT 2022


lenary added a comment.

In D131389#3789376 <https://reviews.llvm.org/D131389#3789376>, @peter.smith wrote:

> A reference I found helpful when looking at this in revision ia of the Arm ARM (https://developer.arm.com/documentation/ddi0487/ia/?lang=en) `Instructions for accessing the PSTATE fields`
>
>   CFINV ; Inverts the value of PSTATE.C
>   MSR DAIFSet, #Imm4 ; Used to set any or all of DAIF to 1
>   MSR DAIFClr, #Imm4 ; Used to clear any or all of DAIF to 0
>   MSR SPSel, #Imm4 ; Used to select the Stack Pointer, between SP_EL0 and SP_ELx
>   MSR UAO, #Imm4 ; Used to set the value of PSTATE.UAO
>   MSR PAN, #Imm4 ; Used to set the value of PSTATE.PAN
>   MSR DIT, #Imm4 ; Used to set the value of PSTATE.DIT
>   MSR SSBS, #Imm4 ; Used to set the value of PSTATE.SSBS
>   MSR TCO, #Imm4 ; Used to set the value of PSTATE.TCO
>   MSR ALLINT, #Imm1 ; Used to set the value of PSTATE.ALLINT
>
> I think the disassembler changes to decode the field as 4-bits looks fine. Changing the assembler to accept 4-bit fields for the fields that are logically on or off, while closer to the architecture, makes it possible to write assembler that isn't going to assemble on the GNU assembler which only accepts 0 or 1. I think that if we change we should at least inform GNU of the change. Personally I don't think that any human will choose to use anything other than 0 or 1 so I don't necessarily think this is going to be a problem in practice.
>
> Hope I've understood that correctly.

I think you have.

I have informed our binutils maintainers, but they're not receptive to updating their implementation. I think we should press ahead anyway.



================
Comment at: llvm/test/MC/AArch64/armv8.1a-pan.s:18
   msr pan, #-1
-  msr pan, #2
   msr pan, w0
----------------
tmatheson wrote:
> Maybe keep the tests with non-0/1 but valid immediates.
these are the "invalid value" tests, but yes, I should have added a check for `msr pan, #15`. will do when I commit.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131389/new/

https://reviews.llvm.org/D131389



More information about the llvm-commits mailing list